Freescale Semiconductor MCF5480 - Manual (Page 868)

MCF548x Reference Manual, Rev. 3
28-14 Freescale Semiconductor
/* Wait for I2SR.IBB (bus busy) to be set */
while ( !(MCF5_I2C_I2SR & MCF_I2C_I2SR_BB) );
28.5.2 Post-Transfer Software Response
Transmission or reception of a byte will set the data transferring bit (ICF) to 1, which indicates one byte
of communication is finished. The interrupt bit (IIF) is set also; an interrupt will be generated if the
interrupt function was enabled during initialization (by setting the IEN bit). Software must clear the IIF bit
in the interrupt service routine first. The ICF bit will be cleared automatically by reading from the data I/O
register (I2DR) in receive mode or writing to I2DR in transmit mode.
Software may service the bus I/O in the main program by monitoring the IIF bit if the interrupt function is
disabled. Note that polling should monitor the IIF bit rather than the ICF bit, because their operation is
different when arbitration is lost.
Also note that when an interrupt occurs at the end of the address cycle, the master will always be in
transmit mode, i.e. the address is transmitted. If master receive mode is required, indicated by the R/W bit
in I2DR, then the MTX bit should be toggled at this stage.
During slave mode address cycles (AAS = 1), the SRW bit in the status register is read to determine the
direction of the subsequent transfer, and the MTX bit is programmed accordingly. For slave mode data
cycles (AAS = 0) the SRW bit is not valid; therefore, the MTX bit in the control register should be read to
determine the direction of the current transfer.
Following is an example of how to monitor IIF instead of ICF:
/*********************************************
* Master TX with interrupt function disabled *
**********************************************/
/* Send the contents of tx_buffer */
for (i=0; i<tx_byte_count; i++)
{
/* Put data to be sent into I2DR */
MCF_I2C_I2DR = tx_buffer[i];
/*Wait for transfer to complete (Poll IIF bit) */
while (!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF) );
/* Clear IIF bit */
MCF_I2C_I2SR &= 0xFD;
}