Freescale Semiconductor MCF5480 - Manual (Page 877)

Introduction
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 29-3
29.1.3.3 FIFO Controller
The FIFO controller implements the data FIFOs in such a way that they can communicate with the
ColdFire core or with the multichannel DMA. There are two physical RAMs that are shared by all of the
FIFO controllers. For maximum performance, the two RAMs can be configured such that one stores
transmit (IN) endpoint data and the other stores receive (OUT) endpoint data. If maximum RAM allocation
flexibility is more important than maximum performance, the RAMs can be configured such that the entire
space is shared by all IN/OUT endpoints. User programmable registers also allow on-the-fly configuration
of individual FIFO sizes and direction.
In order to achieve maximum USB bandwidth, the USB device must be able to provide or receive full
packets of data to or from the USB host immediately upon request. In order to satisfy this requirement,
there is one FIFO for each USB endpoint. The actual FIFO size for each endpoint is programmable.
Typically, BULK and ISOCHRONOUS endpoint FIFOs should be twice the packet size. INTERRUPT and
CONTROL endpoint FIFOs should be programmed to the size of at least one packet.
29.1.3.4 FIFO RAM Manager
The FIFO RAM manager block consists of a memory configuration controller, a FIFO RAM multiplexor,
and a memory request arbitrator. Together, these three functional units allow one or more FIFO modules
to share access to the FIFO memory. While the memory is physically configured as two independent
dual-port SRAM modules, the RAM manager is responsible for partitioning it into individual blocks for
each FIFO controller, and managing the addressing to allow byte, word, or longword access from any byte
offset.
The memory configuration controller partitions the RAM into a set of user specified blocks.
The memory multiplexor and the arbitrator work together to ensure that the correct FIFO has access to the
RAM, and that simultaneous requests to the RAM’s ports are fairly arbitrated.
See the USBCR[RAMSPLIT] bit description and the EPnFRCFGR description for more information on
programming the settings for these blocks.
29.1.3.5 Integrated USB 2.0 Transceiver
The USB 2.0 Device Controller module includes an internal full and high-speed physical layer transceiver
(PHY). The bus interface signals are described below.
29.1.3.5.1 USB Differential Data (USBD+, USBD–)
USBD+ and USBD– are the outputs of the on-chip USB 2.0 physical layer transceiver. They provide
differential data for the USB 2.0 bus.
29.1.3.5.2 USBVBUS
USB cable Vbus monitor input.
29.1.3.5.3 USBRBIAS
Connection for external current setting resistor. This signal should be connected to a 9.1 K Ω +/– 1%
pull-down resistor.