Freescale Semiconductor MCF5480 - Manual (Page 88)

MCF548x Reference Manual, Rev. 3
2-18 Freescale Semiconductor
For burst-inhibited transfers, TSIZ[1:0] changes with each ALE assertion to reflect the next transfer size.
For transfers to port sizes smaller than the transfer size, TSIZ[1:0] indicates the size of the entire transfer
on the first access and the size of the current port transfer on subsequent transfers. For example, for a
longword write to an 8-bit port, TSIZ[1:0] = 2’b00 for the first transaction and 2’b01 for the next three
transactions. If bursting is used and in the case of longword write to an 8-bit port, TSIZ[1:0] is driven to
2’b00 for the entire transfer.
2.2.1.7 Byte Selects (BE/BWE[3:0])
The four byte-enables are multiplexed with the byte-write-enable signals. Each pin can be individually
programmed through the chip select control registers (CSCRs). For each chip select, assertion of
byte-enables for reads and byte-write enables for write cycles can be programmed. Alternatively, users can
program byte-write enables to assert on writes and byte-enable to not assert on reads.
The byte strobe (BE/BWE[3:0]) outputs indicate that data is to be latched or driven onto a byte of the data.
BE/BWE[3:0] signals are asserted only to the memory bytes used during a read or write access.
2.2.1.8 Output Enable (OE)
The output enable signal is sent to the interfacing memory and/or peripheral to enable a read transfer. OE
is asserted only when a chip select matches the current address decode.
2.2.1.9 Transfer Acknowledge (TA)
The external system drives this input to terminate the bus transfer. For write cycles, the processor continues
to drive data at least one clock after FBCSx is negated. During read cycles, the peripheral must continue
to drive data until TA is recognized. The number of wait states is determined either by an internally
programmed auto acknowledgement or the external TA input. If the external TA is used, the peripheral has
total control over the number of wait states.
2.2.2 SDRAM Controller Signals
These signals are used for SDRAM accesses.
2.2.2.1 SDRAM Data Bus (SDDATA[31:0])
SDDATA[31:0] is the bidirectional, non-multiplexed data bus used for SDRAM accesses. Data is sampled
by the MCF548x on the rising edge of SDCLK when in SDR mode, and on both the rising and falling edge
of SDCLK when in DDR mode.
2.2.2.2 SDRAM Address Bus (SDADDR[12:0])
The SDADDR[12:0] signals are the 13-bit address bus used for multiplexed row and column addresses
during SDRAM bus cycles. The address multiplexing supports up to 256 Mbits of SDRAM per chip select.
10 2 bytes (word)
11 16 bytes (line)
Table 2-3. Data Transfer Size (Continued)
TSIZ[1:0] Transfer Size