Freescale Semiconductor MCF5480 - Manual (Page 888)

MCF548x Reference Manual, Rev. 3
29-14 Freescale Semiconductor
29.2.2.5 USB Interrupt Status Register (USBISR)
The USBISR maintains the status of interrupt conditions pertaining to USB functions.
An interrupt, once set, remains set until cleared by writing a 1 to the corresponding bit. Interrupts do not
clear automatically if the event that caused them goes away (for example, if the device enters the
suspended state and then resume signaling starts with no intervention from software, both SUSP and RES
would be set). Writing a 0 has no effect.
If a register write occurs at the same time an interrupt is received, the interrupt takes precedence over the
write.
Table 29-5. DRAMDR Field Descriptions
Bits Name Description
31—8 — Reserved, should be cleared.
7–0 DDAT Descriptor data. For descriptor access, software programs address into the DADR[9:0] bits in the
DRAMCR register and follow with a read or write to the DRAMDR register to complete the access.
Upon the read/write access, the address in DADR[9:0] will increment automatically.
User access to this register is only allowed when the USBCR[EN] bit is cleared. Accesses at other
times are ignored and reads are undefined.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R Uninitialized
W
Reset Uninitialized
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R Uninitialized MSOF SOF RSTSTOP UPDSOF RES SUSP FTUNLCK ISOERR
W
Reset Uninitialized 0 0 0 0 0 0 0 0
Reg
Addr
MBAR + 0xB410
Figure 29-6. USB Interrupt Status Register (USBISR)
Table 29-6. USBISR Field Descriptions
Bits Name Description
31—8 — Reserved, should be cleared.
7 MSOF Missed start of frame interrupt.
0 No missed start of frame.
1 An SOF interrupt was set, but not cleared before the next one was received.
6 SOF Start of frame interrupt.
0 No start of frame received
1 A start of frame token has been received by the USB. The USB frame number is current.