Freescale Semiconductor MCF5480 - Manual (Page 90)

MCF548x Reference Manual, Rev. 3
2-20 Freescale Semiconductor
2.2.2.14 SDRAM Reference Voltage (VREF)
This is the input reference voltage for differential SSTL_2 inputs. It is used in both DDR and SDR modes.
2.2.3 PCI Controller Signals
2.2.3.1 PCI Address/Data Bus (PCIAD[31:0])
The PCIAD[31:0] lines are a time-multiplexed address data bus. The address is presented on the bus during
the address phase while the data is presented on the bus during one or more data phases.
If the FlexBus is used in 32-bit address or 32-bit data non-multiplexed mode, PCIAD[31:0] are used as a
32-bit address for FlexBus transfers.
2.2.3.2 Command/Byte Enables (PCICXBE[3:0])
The PCICXBE[3:0] lines are time-multiplexed. The PCI command is presented during the address phase,
and the byte enables are presented during the data phase.
2.2.3.3 Device Select (PCIDEVSEL)
The PCIDEVSEL signal is asserted active low when the MCF548x decodes that it is the target of a PCI
transaction from the address presented on the PCI bus during the address phase.
2.2.3.4 Frame (PCIFRM)
The PCIFRM signal is asserted by a PCI initiator to indicate the beginning of a transaction. It is negated
when the initiator is ready to complete the final data phase.
2.2.3.5 Initialization Device Select (PCIIDSEL)
The PCIIDSEL signal is asserted during a PCI type-0 configuration cycle to address the PCI configuration
header.
2.2.3.6 Initiator Ready (PCIIRDY)
The PCIIRDY signal is asserted to indicate that the PCI initiator is ready to transfer data. During a write
operation, assertion indicates that the master is driving valid data on the bus. During a read operation,
assertion indicates that the master is ready to accept data.
2.2.3.7 Parity (PCIPAR)
The PCIPAR signal indicates the parity of data on the PCIAD[31:0] and PCICXBE[3:0] lines.
2.2.3.8 Parity Error (PCIPERR)
The PCIPERR signal is asserted when a data phase parity error is detected if enabled.