Freescale Semiconductor MCF5480 - Manual (Page 91)

MCF548x External Signals
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 2-21
2.2.3.9 Reset (PCIRESET)
The PCIRESET signal is asserted active low by MCF548x to reset the PCI bus. This signal is asserted after
the MCF548x is reset and must be negated to enable usage of the PCI bus.
2.2.3.10 System Error (PCISERR)
The PCISERR signal, if enabled, is asserted when an address phase parity error is detected.
2.2.3.11 Stop (PCISTOP)
The PCISTOP signal is asserted by the currently addressed target to indicate that it wishes to stop the
current transaction.
2.2.3.12 Target Ready (PCITRDY)
The PCITRDY signal is asserted by the currently addressed target to indicate that it is ready to complete
the current data phase.
2.2.3.13 External Bus Grant (PCIBG[4:1])
The PCIBG signal is asserted to an external master to give it control of the PCI bus. If the internal PCI
arbiter is enabled, it asserts one of the PCIBG[4:1] lines to grant ownership of the PCI bus to an external
master. When the PCI arbiter module is disabled, PCIBG[4:1] is driven high and should be ignored.
2.2.3.14 External Bus Grant/Request Output (PCIBG0/PCIREQOUT)
The PCIBG0 signal is asserted to external master device 0 to give it control of the PCI bus. When the PCI
arbiter module is disabled, the signal operates as the PCIREQOUT output. It is asserted when the
MCF548x needs to initiate a PCI transaction.
2.2.3.15 External Bus Request (PCIBR[4:0])
The PCIBR signal is asserted by an external PCI master when it requires access to the PCI bus.
2.2.3.16 External Request/Grant Input (PCIBR0/PCIGNTIN)
The PCIBR0 signal is asserted by external PCI master device 0 when it requires access to the PCI bus.
When the internal PCI arbiter module is disabled, this signal is used as a grant input for the PCI bus,
PCIGNTIN. It is driven by an external PCI arbiter.
2.2.4 Interrupt Control Signals
The interrupt control signals supply the external interrupt level to the MCF548x device.
2.2.4.1 Interrupt Request (IRQ[7:1])
The IRQ[7:1] signals are the external interrupt inputs.