Freescale Semiconductor MCF5480 - Manual (Page 923)

Software Interface
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 29-49
Download of the descriptor data consists of the following steps:
1. Verify that the USBCR[RAMEN] bit is clear. This ensures that the datapath to the descriptor RAM
is open to the application.
2. Write the starting address of the descriptors into the DADR field of the DRAMCR. The address
written to this register is the address of the descriptors within the descriptor RAM.
3. Write each byte of the descriptor table to the DDAT field of the DRAMDR. This register
increments automatically at each register access (read or write).
29.4.1.2 USB Interrupt Register
If the application makes use of the interrupt registers, then the specific interrupts to be used must be
enabled. During a reset, all interrupts revert to the masked state. USB global interrupts (affecting whole
module) are programmed separately from those affecting a single endpoint.
29.4.1.3 Endpoint Registers
For each endpoint, the characteristics of the FIFO and a number of interrupt sources may be programmed.
The integrator must program the following registers:
• USB internal endpoint context registers USB endpoint status settings (EPnSTAT).
• USB endpoint interrupt mask (EPnIMR)
• Separate interrupt registers are provided for each hardware FIFO. Enable the interrupts pertaining
to the application by writing a 0 to the mask bit for that interrupt.
• Endpoint FIFO controller configuration (EPnFCR)
• Each FIFO is programmed based for the type of data transmission used by the endpoint
• FIFO alarm register (EPnFAR).
• For bulk traffic (EPnFCR[FRAME] = 1), the alarm level is normally programmed to a multiple of
the USB packet size (that is, for 8-byte packets and a 16-byte FIFO, the alarm would be
programmed to 8 bytes) to allow the DMA request lines to request full packets. For single buffered
endpoints (packet size = 8, FIFO depth = 8 bytes), the alarm is normally programmed to 0. For
isochronous traffic, the alarm is programmed to allow streaming operation to occur on the
isochronous endpoint.
29.4.1.3.1 USB Endpoint to FIFO Mapping
The USB protocol recognizes up to 31 endpoints on a USB device. The endpoint numbers available on a
specific USB device can vary based on the functionality present in the device, along with the configuration
and alternate interfaces selected at any given time. Regardless of the “logical” endpoint number
programmed in the interface descriptors, some hardware must be associated with each endpoint.
Each hardware endpoint consists of a single FIFO which can be programmed independently for depth,
direction, frame mode, and low/high alarms.
• Endpoint direction is defined via the EPnSTAT register for each endpoint. FIFO characteristics are
programmed via the EPnFCR and EPnFAR. These settings should be configured before the device
responds to a request from the host.