Freescale Semiconductor MCF5480 - Manual (Page 926)

MCF548x Reference Manual, Rev. 3
29-52 Freescale Semiconductor
2. On receiving EOF interrupt, prepare to read a complete packet of data. Clear the EOF interrupt so
that software will receive notification of the next frame.
3. Read the EPnFDR to read in the next piece of data.
4. Read the EPnFSR to get the end of frame status bits. If the end of frame bit is set for the current
transfer, then stop reading data.
5. Go back to step 3.
29.4.3.3.1 Programming the FIFO Controller
The FIFO controller module has two modes of operation: frame and non-frame. For the USB application,
normally only frame mode is used.
In frame mode, the FIFO controller can handle automatic hardware retry of bad packets. This mode is used
for bulk, control, and interrupt endpoints. During device initialization, the user should configure the FIFOs
via the EPnFCR for frame mode. Data flow is controlled with the end-of-frame (EOF) and end-of-transfer
(EOT) interrupts, or with the internal DMA request lines.
29.4.3.4 USB Transfers
Data transfers on the USB are composed of one or more packets. Instead of maintaining a transfer count,
the USB host and device send groups of packets to each other in units called transfers. In a transfer, all
packets are the same size, except the last one. The last packet in a transfer will be a short packet, as small
as 0 bytes in the case that the last data byte ends on a packet boundary.
This section describes how data transfers work from both the device to the host, and from the host to the
device.
29.4.3.4.1 Data Transfers to the Host
Given an arbitrary sized block of data to be sent to the host, break it into a number of packets sized at the
maximum packet size of the target endpoint.
If the number of packets is an integer, then the transfer ends on a packet boundary. A zero length packet
will be required to terminate the transfer. If the number of packets is not an integer, then the last packet of
the transfer will be a short packet and no zero length packet is required.
For each packet in the transfer, write the data to the EPnFDR. The last byte in each packet must be tagged
with the end of frame marker via the EPnFCR (if using the DMA, this is taken care of via the DMA service
request lines). Monitor the FIFOLO interrupt, EOF interrupt, or DMA service requests to determine when
the FIFO can accept another packet.
After the last byte of the transfer has been written to the FIFO, if a zero length packet is required to
terminate the transfer, then set the CCOMP/TXZERO bit in the EPnOUTSR or EPnINSR.
29.4.3.4.2 Data Transfers to the Device
The length of data transfer from the host is generally not known in advance. The device receives a
continuous stream of packets and uses the EOT interrupt to determine when the transfer ended.
Software on the device monitors the EOF interrupt and/or the DMA requests to manage packet traffic.
Each time a packet is received, the device must pull the data from the FIFO. Each time an end of frame is
transferred from the USB module into the data FIFO, the EOF interrupt asserts. At the end of a complete
transfer, the EOT interrupt asserts. Until the CPU has serviced the EOT interrupt, the device will NAK any