Freescale Semiconductor MCF5480 - Manual (Page 927)

Software Interface
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 29-53
further requests from the host. This guarantees that data from two different transfers will never get
intermixed within the FIFO.
NOTE
The DMA extensions do not define a zero length frame. Thus, it is necessary
to have the CPU monitor the EOT interrupts and use them as a basis for
delineating individual transfers. USB traffic flow is halted until the EOT
interrupt has been serviced to ensure that data from different data transfers
does not get mixed-up in the FIFOs.
29.4.3.5 Control Transfers
The USB 2.0 Device Controller provides one control endpoint, endpoint zero. The USB host sends
commands to the device via control transfers. Control transfers consist of up to three distinct phases. Each
control transfer begins with a setup phase, followed by an optional data phase, and is completed with a
status phase.
29.4.3.5.1 Default Control Pipe
Every USB device is required to implement a control endpoint, the Default Control Pipe, on endpoint zero
(EP0). The USB host uses the default endpoint to read the device descriptors and to configure the device.
29.4.3.5.2 Device Requests
The Setup packet of a control transfer contains the request from the host and the request’s parameters.
Some of these requests are recognized by the USB device controller as standard device requests, while
others are non-standard requests classified as vendor-specific or class-specific. The USB device controller
automatically processes the following standard requests without any application intervention:
• SET_FEATURE, CLEAR_FEATURE
• GET_CONFIGURATION
• GET_INTERFACE
• GET_STATUS
• SET_ADDRESS
The following requests require application intervention:
• SET_CONFIGURATION
• SET_DESCRIPTOR, GET_DESCRIPTOR
• SET_INTERFACE
• Non-standard requests: vendor-specific or class-specific
The GET_DESCRIPTOR request requires a minimal amount of software intervention. See
Section 29.2.2.3, “USB Descriptor RAM Control Register (DRAMCR) ”, for more details.
Command processing of the remaining requests that require application intervention should occur in the
following order:
1. A SETUP packet is received on EP0 and the USBAISR[SETUP] bit will be set.
2. Read 8 bytes from the BMRTR, BRTR, WVALUER, WINDEXR, and WLENGTHR registers and
decode the command.
3. Clear the USBAISR[SETUP] interrupt.