Freescale Semiconductor MCF5480 - Manual (Page 928)

MCF548x Reference Manual, Rev. 3
29-54 Freescale Semiconductor
4. Handle the request appropriately. If a data transfer is implied by the command, set up and perform
the data transfer. Be careful not to send back more bytes to the USB host than were requested in
the wLength field of the SETUP packet. The USB device controller hardware does not check for
incorrect data phase length. The EOT interrupt will assert on completion of the data phase.
5. Set CCOMP in either the EPnOUTSR or EPnINSR and TXZERO in EPnOUTSR or EPnINSR to
complete the transfer. If needed, also set the PSTALL bit in either EPnOUTSR or EPnINSR to
indicate error status. The USB device controller will generate appropriate handshakes on the USB
to implement the status phase.
29.4.3.6 Bulk Traffic
Bulk traffic guarantees the error-free delivery of data in the order that it was sent, but the rate of transfer
is not guaranteed. Bandwidth is allocated to bulk, interrupt, and control packets based on the bandwidth
usage policy of the USB host.
29.4.3.6.1 Bulk OUT
For OUT transfers (from host to device), internal logic marks the start of packet location in the FIFO. If a
transfer does not complete without errors, the logic will force the FIFO to back up to the start of the current
packet and try again. No software intervention is required to handle packet retries.
User software reads packets from the FIFOs as they appear and stops when an EOT interrupt is received.
To enable further data transfers, software services and clears the pending interrupts (EOF or EOT), then
waits for the next transfer to begin.
29.4.3.6.2 Bulk IN
For IN transfers (from device to host), software tags the last byte in a packet to mark the end of frame. If
a transfer does not complete without errors, hardware will automatically force the FIFO to back up to the
start of the current packet and re-send the data. User software is expected to write data to the FIFO data
register in units of the associated endpoint’s maximum packet size. The end of frame may be indicated via
the WFR bit in the endpoint FIFO control register (EPnFCR).
In the USB protocol, the last packet in a transfer is allowed to be short (smaller than endpoint’s maximum
packet size) or even zero length. In order to indicate a zero length packet, the software should set the
CCOMP/TXZERO bit in the EPnOUTSR or EPnINSR.
29.4.3.7 Interrupt Traffic
Interrupt endpoints are a special case of bulk traffic. Interrupt endpoints are serviced on a periodic basis
by the USB host. Interrupt endpoints are guaranteed to transfer one packet per polling interval. Thus, an
endpoint with an 8-byte packet size and serviced every 2 ms would move 16 Kbps across the USB.
The only difference between interrupt transfers and bulk transfers from the device standpoint is that every
time an interrupt packet is transferred, regardless of size, the EOT interrupt asserts. For OUT endpoints,
the device driver software must service this interrupt before the next interrupt servicing interval to prevent
the device from NAK’ing the poll.
Device driver software must be careful that the interrupt endpoint polling interval is longer than the
device’s interrupt service latency.