Freescale Semiconductor MCF5480 - Manual (Page 932)

MCF548x Reference Manual, Rev. 3
30-2 Freescale Semiconductor
Figure 30-1. FEC Block Diagram
30.1.3 Overview
The Fast Ethernet Controller is designed to support both 10 and 100 Mbps Ethernet/IEEE 802.3 networks.
An external transceiver interface and transceiver function are required to complete the interface to the
media. The FEC supports three different standard MAC-PHY (physical) interfaces for connection to an
external Ethernet transceiver. The FEC supports the 10/100 Mbps MII and the 10 Mbps-only 7-wire
interface, which uses a subset of the MII pins. The user controls the FEC by writing the control registers
within the CSR (control and status register) block. The CSR provides global control (e.g. Ethernet reset
and enable) and interrupt handling registers.
The MII block provides a serial channel for control/status communication with the external physical layer
device (transceiver). This serial channel consists of the EMDC (management data clock) and EMDIO
(management data input/output) lines of the MII interface.
The transmit and receive blocks provide the Ethernet MAC functionality (with some assist from
microcode). The transmit and receive FIFOs are 1024 bytes each.
The message information block (MIB) maintains counters for a variety of network events and statistics. It
is not necessary for operation of the FEC but provides valuable counters for network management. The
counters supported are the RMON (RFC 1757) Ethernet Statistics group and some of the IEEE 802.3
counters. See Section 30.3.3, “MIB Block Counters Memory Map ,” for more information.
I/O
Pad
EnMDIO EnMDC
EnTXEN
EnTXD[3:0]
EnTXER
EnTXCLK
EnCRS
EnRXCLK
EnRXDV
EnRXD[3:0]
EnRXER
MII/7-Wire
Data Option
EnCOL
FEC
CSR
Slave
Interface
MII
MIB
Counters
Transmit Receive
FIFO
Transmit
FIFO
Receive
FIFO Controller Interr
upt
E nMDIO
E nMDEN
E nMDIO
IP Bus
Comm Bus