Freescale Semiconductor MCF5480 - Manual (Page 935)

External Signals
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 30-5
30.2.5 Transmit Error (EnTXER)
Assertion of this output signal for one or more clock cycles while EnTXEN is asserted shall cause the PHY
to transmit one or more illegal symbols. Asserting EnTXER has no affect when operating at 10 Mbps or
when EnTXEN is de-asserted This signal transitions synchronously with respect to EnTXCLK.
30.2.6 Receive Data Valid (EnRXDV)
When this input signal is asserted, the PHY is indicating that a valid nibble is present on the MII. This
signal shall remain asserted from the first recovered nibble of the frame through the last nibble. Assertion
of EnRXDV must start no later than the Start of Frame delimiter (SFD), and exclude any End of Frame
delimiter (EOF).
30.2.7 Receive Data[3:0] (EnRXD[3:0])
EnRXD[3:0] represents a nibble of data to be transferred from the PHY to the MAC when EnRXDV is
asserted. A completely formed SFD must be passed across the MII. When EnRXDV is not asserted,
EnRXD has no meaning. There is an exception to this which is explained later. Table 30-3 summarizes the
permissible encoding of EnRXD. EnRXD0 is used for serial data in 7-wire mode.
30.2.8 Receive Error (EnRXER)
When EnRXER and EnRXDV are asserted, the PHY has detected an error in the current frame. When
EnRXDV is not asserted, EnRXER shall have no affect. This signal transitions synchronously with
EnRXCLK
30.2.9 Carrier Sense (EnCRS)
This input signal is asserted when the transmit or receive medium is not idle. In the event of a collision,
EnCRS will remain asserted through the duration of the collision. This signal is not required to transition
synchronously with EnTXCLK or EnRXCLK.
30.2.10 Collision (EnCOL)
This input signal is asserted upon detection of a collision, and will remain asserted while the collision
persists. The behavior of this signal is not specified when in Full Duplex mode. This signal is not required
to transition synchronously with EnTXCLK or EnRXCLK.
30.2.11 Management Data Clock (EnMDC)
This signal provides a timing reference to the PHY for data transfers on the EnMDIO signal. EnMDC is
aperiodic, and has no maximum high or low times. The minimum high and low times is 160ns, with the
minimum period being 400ns.
30.2.12 Management Data (EnMDIO)
This signal transfers control/status information between the PHY and MAC. It transitions synchronously
to EnMDC. The EnMDIO pin is a bidirectional pin.
Table 30-2 below provides the interpretation of the possible encodings of EnTXEN, EnTXER.