Freescale Semiconductor MCF5480 - Manual (Page 945)

Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 30-15
To perform a read or write operation on the MII Management Interface, the MMFR register must be
written by the user. To generate a valid read or write management frame, the ST field must be written with
a 01 pattern, and the TA field must be written with a 10. If other patterns are written to these fields, a frame
will be generated but will not comply with the IEEE 802.3 MII definition.
If the MMFR is written while frame generation is in progress, the frame contents will be altered. Software
should use the MII interrupt to avoid writing to the MMFR register while frame generation is in progress.
30.3.3.4.1 Generating a Write Frame
To generate an IEEE 802.3-compliant MII Management Interface write frame (write to a PHY register),
the user must write {01 01 PHYAD REGAD 10 DATA} to the MMFR register. Writing this pattern will
cause the control logic to shift out the data in the MMFR register following a preamble generated by the
control state machine. During this time the contents of the MMFR register will be altered as the contents
are serially shifted and will be unpredictable if read by the user. Once the write management frame
operation has completed, the MII interrupt will be generated. At this time the contents of the MMFR
register will match the original value written.
30.3.3.4.2 Generating a Read Frame
To generate an MII Management Interface read frame (read a PHY register) the user must write {01 10
PHYAD REGAD 10 XXXX} to the MMFR register (the content of the DATA field is a don’t care). Writing
this pattern will cause the control logic to shift out the data in the MMFR register following a preamble
generated by the control state machine. During this time the contents of the MMFR register will be altered
as the contents are serially shifted, and will be unpredictable if read by the user. Once the read management
frame operation has completed, the MII interrupt will be generated. At this time the contents of the MMFR
register will match the original value written except for the DATA field whose contents have been replaced
by the value read from the PHY register.
30.3.3.5 MII Speed Control Register (MSCR)
The MSCR provides control of the MII clock (EMDC signal) frequency and allows dropping the preamble
on the MII management frame.
27–23 PA PHY address. This field specifies one of up to 32 attached PHY devices.
22–18 RA Register address. This field specifies one of up to 32 registers within the specified PHY device.
17–16 TA Turn around. This field must be programmed to 0x10 to generate a valid MII management frame.
15–0 DATA Management frame data. This is the field for data to be written to or read from the PHY register.
Table 30-10. MMFR Field Descriptions (Continued)
Bit Name Description