Freescale Semiconductor MCF5480 - Manual (Page 948)

MCF548x Reference Manual, Rev. 3
30-18 Freescale Semiconductor
30.3.3.8 Receive Hash Register (RHR)
This read only register provides address recognition information from the receive block about the frame
currently being received.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R 0 0 0 0 0 MAX_FL
W
Reset 0 0 0 0 0 1 0 1 1 1 1 0 1 1 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0 0 0 0 0 0 0 0 0 FCE BC_REJ PROM MII_
MODE
DRT LOOP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Reg
Addr
MBAR + 0x9084 (FEC0), 0x9884 (FEC1)
Figure 30-8. Receive Control Register (RCR)
Table 30-14. RCR Field Descriptions
Bits Name Description
31–27 — Reserved, should be cleared.
26–16 MAX_FL Maximum frame length. Resets to decimal 1518. Length is measured starting at DA and includes the
CRC at the end of the frame. Transmit frames longer than MAX_FL will cause the BABT interrupt to
occur. Receive frames longer than MAX_FL will cause the BABR interrupt to occur. The
recommended default value to be programmed by the user is 1518 or 1522 (if VLAN Tags are
supported).
15–6 — Reserved, should be cleared.
5 FCE Flow control enable. If asserted, the receiver will detect PAUSE frames. Upon PAUSE frame
detection, the transmitter will stop transmitting data frames for a given duration.
4 BC_REJ Broadcast frame reject. If asserted, frames with DA (destination address) = FF_FF_FF_FF_FF_FF
will be rejected unless the PROM bit is set. If both BC_REJ and PROM = 1, then frames with
broadcast DA will be accepted.
3 PROM Promiscuous mode. All frames are accepted regardless of address matching.
2 MII_MODE Media independent interface mode. Selects external interface mode. Setting this bit to one selects
MII mode, setting this bit equal to zero selects 7-wire mode (used only for serial 10 Mbps). This bit
controls the interface mode for both transmit and receive blocks.
1 DRT Disable receive on transmit.
0 Receive path operates independently of transmit (use for full duplex or to monitor transmit activity
in half duplex mode).
1 Disable reception of frames while transmitting (normally used for half duplex mode).
0 LOOP Internal loopback. If set, transmitted frames are looped back internal to the device and the transmit
output signals are not asserted. The system clock is substituted for the ETXCLK when LOOP is
asserted. DRT must be set to zero when asserting LOOP.