Freescale Semiconductor MCF5480 - Manual (Page 95)

MCF548x External Signals
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 2-25
2.2.7.2 Management Data Clock (E0MDC, E1MDC)
EMDC is an output clock that provides a timing reference to the PHY for data transfers on the EMDIO
signal; it applies to MII mode operation.
2.2.7.3 Transmit Clock (E0TXCLK, E1TXCLK)
This is an input clock that provides a timing reference for ETXEN, ETXD[3:0], and ETXER.
2.2.7.4 Transmit Enable (E0TXEN, E1TXEN)
The transmit enable (ETXEN) output indicates when valid nibbles are present on the MII. This signal is
asserted with the first nibble of a preamble and is negated before the first ETXCLK following the final
nibble of the frame.
2.2.7.5 Transmit Data 0 (E0TXD0, E1TXD0)
ETXD0 is the serial output Ethernet data and is only valid during the assertion of ETXEN. This signal is
used for 10 Mbps Ethernet data. This signal is also used for MII mode data in conjunction with ETXD[3:1].
2.2.7.6 Collision (E0COL, E1COL)
The ECOL input is asserted upon detection of a collision and remains asserted while the collision persists.
This signal is not defined for full-duplex mode.
2.2.7.7 Receive Clock (E0RXCLK, E1RXCLK)
The receive clock (ERXCLK) input provides a timing reference for ERXDV, ERXD[3:0], and ERXER.
2.2.7.8 Receive Data Valid (E0RXDV, E1RXDV)
Asserting the receive data valid (ERXDV) input indicates that the PHY has valid nibbles present on the
MII. ERXDV should remain asserted from the first recovered nibble of the frame through to the last nibble.
Assertion of ERXDV must start no later than the SFD and exclude any EOF.
2.2.7.9 Receive Data 0 (E0RXD0, E1RXD0)
ERXD0 is the Ethernet input data transferred from the PHY to the media-access controller when ERXDV
is asserted. This signal is used for 10 Mbps Ethernet data. This signal is also used for MII mode Ethernet
data in conjunction with ERXD[3:1].
2.2.7.10 Carrier Receive Sense (E0CRS, E1CRS)
ECRS is an input signal that, when asserted, signals that transmit or receive medium is not idle, and applies
to MII mode operation.
2.2.7.11 Transmit Data 1–3 (E0TXD[3:1], E1TXD[3:1])
These pins contain the serial output Ethernet data and are valid only during assertion of ETXEN in MII
mode.