Freescale Semiconductor MCF5480 - Manual (Page 951)

Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 30-21
30.3.3.11 Physical Address High Register (PAHR)
The PAHR is written by the user. This register contains the upper 16 bits (bytes 4 and 5) of the 48-bit
address used in the address recognition process to compare with the DA (destination address) field of
receive frames with an individual DA. In addition, this register is used in bytes 4 and 5 of the 6-byte Source
Address field when transmitting PAUSE frames. Bits 15:0 of PAHR contain a constant type field (0x8808)
used for transmission of PAUSE frames. This register is not reset and bits 31:16 must be initialized by the
user.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R PADDR1
W
Reset Uninitialized
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R PADDR1
W
Reset Uninitialized
Reg
Addr
MBAR + 0x90E4 (FEC0), 0x98E4 (FEC1)
Figure 30-11. Physical Address Low Register (PALR)
Table 30-17. PALR Field Descriptions
Bits Name Description
31–0 PADDR1 Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8) and 3 (bits 7:0) of the 6-byte individual
address to be used for exact match, and the Source Address field in PAUSE frames.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R PADDR2
W
Reset Uninitialized
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R TYPE
W
Reset 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0
Reg
Addr
MBAR + 0x90E8 (FEC0), 0x98E8 (FEC1)
Figure 30-12. Physical Address High Register (PAHR)