Freescale Semiconductor MCF5480 - Manual (Page 953)

Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 30-23
30.3.3.14 Individual Address Lower Register (IALR)
The IALR register is written by the user. This register contains the lower 32 bits of the 64-bit individual
address hash table used in the address recognition process to check for possible match with the destination
address (DA) field of receive frames with an individual DA. This register is not reset and must be
initialized by the user.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R IADDR1
W
Reset Uninitialized
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R IADDR1
W
Reset Uninitialized
Reg
Addr
MBAR + 0x9118 (FEC0), 0x9918 (FEC1)
Figure 30-16. Individual Address Upper Register (IAUR)
Table 30-20. IAUR Field Descriptions
Bits Name Descriptions
31–0 IADDR1 Individual Address Upper - The upper 32 bits of the 64-bit hash table used in the address
recognition process for receive frames with a unicast address. Bit 31 of IADDR1 contains
hash index bit 63. Bit 0 of IADDR1 contains hash index bit 32.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R IADDR2
W
Reset Uninitialized
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R IADDR2
W
Reset Uninitialized
Reg
Addr
MBAR + 0x911C (FEC0), 0x991C (FEC1)
Figure 30-17. Individual Address Lower Register (IALR)