28 fec transmit fifo control register (fectfcr), Fec transmit fifo control register (fectfcr) -36 – Freescale Semiconductor MCF5480 User Manual
Page 966
MCF548x Reference Manual, Rev. 3
30-36
Freescale Semiconductor
30.3.3.28 FEC Transmit FIFO Control Register (FECTFCR)
The FIFO transmit control register provides programmability of FIFO behaviors, including last transfer
granularity and frame operation. Last transfer granularity allows the user to control when the FIFO
controller stops requesting data transfers through the FIFO alarm by modifying the clearing point of the
alarm, ensuring the data stream is stopped at a valid point, or there remains enough space in the FIFO to
unload the input data pipeline. Additional explanation of this field can be found below. The frame mode
enable (FRMEN) bit of the control register provides a capability to enable and control the FIFO
controller’s ability to view data on a packetized basis. Frame mode overrides the FIFO granularity bits, by
setting the FECTFSR[FRMRDY] bit. The bit definitions for this register are shown in
, and
the fields are further defined in the field descriptions of
.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
WCTL WFR TIMER FRMEN
GR
IP_
MSK
FAE_
MSK
1
UF_
MSK
OF_
MSK
TXW_
MASK
0
0
W
Reset
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
COUNTER
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
MBAR + 0x91AC (FEC0), 0x99AC (FEC1)
Figure 30-31. FEC Transmit FIFO Control Register (FECTFCR)
Table 30-35. FECTFCR Field Descriptions
Bits
Name
Descriptions
31
—
Reserved, should be cleared.
30
WCTL
Write control. When this bit is set, the FIFO controller assumes the next write to its data port
contains control information for the peripheral, and will tag the incoming data accordingly. This bit
is automatically cleared by a write to the data port.
29
WFR
Write frame. When this bit is set, the FIFO controller assumes the next write to its data port is the
end of a frame, and will tag the incoming data accordingly. This bit is automatically cleared by a
write to the data port.
28
TIMER
Timer mode enable. When this bit is set, the FIFO controller will suppress a frame ready request
for service from occuring until the timer expires. The timer period can be programmed using the
COUNTER[15:0] bits. A request for service will be made every (COUNTER[15:0] * 64) cycles as
long as a valid frame exists in the FIFO. Alarm requests are not affected by this mode. Further,
the timer is restarted anytime a read or a write to the FIFO Data register occurs. This indicates
that either the FIFO currently has the DMA’s attention or that data is still being transfered and that
there is the possibility that a naturally generated alarm will occur. This bit is only meaningful when
frame mode is enabled via the FRMEN bit.
27
FRMEN
Frame mode enable. When this bit is set, the FIFO controller monitors frame done information
from the peripheral or multi-channel DMA. Setting this bit also enables the other frame control bits
in this register, as well as other frame functions. This bit must be set to use frame functions.