Freescale Semiconductor MCF5480 - Manual (Page 98)

MCF548x Reference Manual, Rev. 3
2-28 Freescale Semiconductor
2.2.11.1 Serial Clock (SCL)
This bidirectional open-drain signal is the clock signal for the I
2
C interface. It is either driven by the I
2
C
module when the bus is in master mode, or it becomes the clock input when the I
2
C is in slave mode.
2.2.11.2 Serial Data (SDA)
This bidirectional open-drain signal is the data input/output for the I
2
C interface.
2.2.12 PSC Module Signals
The PSC modules use the signals in this section. The baud rate clock inputs are not supported.
2.2.12.1 Transmit Serial Data Output (PSC0TXD, PSC1TXD, PSC2TXD, PSC3TXD)
PSCnTXD are the transmitter serial data outputs for the PSC modules. The output is held high (mark
condition) when the transmitter is disabled, idle, or in the local loopback mode. The PSCxTXD pins can
be programmed to be driven low (break status) by a command.
2.2.12.2 Receive Serial Data Input (PSC0RXD, PSC1RXD, PSC2RXD, PSC3RXD)
PSCnRXD are the receiver serial data inputs for the PSC modules. When the PSC clock is stopped for
power-down mode, any transition on the pins restarts them.
2.2.12.3 Clear-to-Send (PSCnCTS/PSCBCLK)
These signals either operate as the clear-to-send input signals in UART mode or the bit clock input signals
in modem modes and IrDA modes. In MIR and FIR mode, the frequency is a multiple of the input bit clock
frequency, and the bit clock frequency should be within +/-0.1% and +/-0.01% of the ideal one,
respectively.
2.2.12.4 Request-to-Send (PSCnRTS/PSCFSYNC)
The PSCnRTS signals act as transmitter request-to-send (RTS) outputs in UART mode, the frame sync
input in modem8 and modem16 modes, or the RTS output (which acts as frame sync) in AC97 modem
mode.
2.2.13 DMA Controller Module Signals
The DMA controller module uses the signals in the following subsections to provide external requests for
either a source or destination.
2.2.13.1 DMA Request (DREQ[1:0])
These inputs are asserted by a peripheral device to request an operand transfer between that peripheral and
memory by either channel 0 or 1 of the on-chip DMA module.
2.2.13.2 DMA Acknowledge (DACK[1:0])
These outputs are asserted to acknowledge that a DMA request has been recognized.