Freescale Semiconductor MCF5480 - Manual (Page 982)

MCF548x Reference Manual, Rev. 3
30-52 Freescale Semiconductor
30.4.8 Full Duplex Flow Control
Full-duplex flow control allows the user to transmit pause frames and to detect received pause frames.
Upon detection of a pause frame, MAC data frame transmission stops for a given pause duration.
To enable pause frame detection, the FEC must operate in full-duplex mode (TCR[FDEN] asserted) and
flow control enable (RCR[FCE]) must be asserted. The FEC detects a pause frame when the fields of the
incoming frame match the pause frame specifications, as shown in the table below. In addition, the receive
status associated with the frame should indicate that the frame is valid.
Pause frame detection is performed by the receive module. The FEC runs an address recognition
subroutine to detect the specified pause frame destination address, while the receiver detects the type and
opcode pause frame fields. On detection of a pause frame, TCR[GTS] is asserted by the FEC internally.
When transmission has paused, the EIR[GRA] interrupt is asserted and the pause timer begins to
increment. The pause timer increments once every slot time ( 512 bit times ), until OPD[PAUSE_DUR]
slot times have expired. On OPD[PAUSE_DUR] expiration, TCR[GTS] is deasserted allowing MAC data
frame transmission to resume. Note that the receive flow control pause (TCR[RFC_PAUSE]) status bit is
asserted while the transmitter is paused due to reception of a pause frame.
To transmit a pause frame, the FEC must operate in full-duplex mode and the user must assert flow control
pause (TCR[TFC_PAUSE]). On assertion of transmit flow control pause (TCR[TFC_PAUSE]), the
transmitter asserts TCR[GTS] internally. When the transmission of data frames stops, the EIR[GRA]
(graceful stop complete) interrupt asserts. Following EIR[GRA] assertion, the pause frame is transmitted.
On completion of pause frame transmission, flow control pause (TCR[TFC_PAUSE]) and TCR[GTS] are
deasserted internally.
During pause frame transmission, the transmit hardware places data into the transmit data stream from the
registers shown in the table below.
FD:FF:FF:FF:FF:FF 0x3C 60
DD:FF:FF:FF:FF:FF 0x3D 61
9D:FF:FF:FF:FF:FF 0x3E 62
BD:FF:FF:FF:FF:FF 0x3F 63
Table 30-50. PAUSE Frame Field Specification
PAUSE Frame Fields Register Contents
48-bit Destination Address 01:80:C2:00:00:01 or Physical Address
48-bit Source Address Any
16-bit Type 0x8808
16-bit Opcode 0x0001
16-bit PAUSE Duration 0x0000 to 0xFFFF
Table 30-49. Destination Address to 6-Bit Hash (Continued)
48-bit Destination
Address
6-bit Hash (in
Hex)
Hash Decimal
Value