Freescale Semiconductor MCF5480 - Manual (Page 983)

Functional Description
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 30-53
The user must specify the desired pause duration in the OPD register.
Note that when the transmitter is paused due to receiver/microcontroller pause frame detection, transmit
flow control pause (TCR[TFC_PAUSE]) still may be asserted and will cause the transmission of a single
pause frame. In this case, the EIR[GRA] interrupt will not be asserted.
30.4.9 Inter-Packet Gap (IPG) Time
The minimum inter-packet gap time for back-to-back transmission is 96 bit times. After completing a
transmission or after the backoff algorithm completes, the transmitter waits for carrier sense to be negated
before starting its 96 bit time IPG counter. Frame transmission may begin 96 bit times after carrier sense
is negated if it stays negated for at least 60 bit times. If carrier sense asserts during the last 36 bit times, it
will be ignored and a collision will occur.
The receiver receives back-to-back frames with a minimum spacing of at least 28 bit times. If an IPG
between receive frames is less than 28 bit times, the following frame may be discarded by the receiver.
30.4.10 Collision Handling
If a collision occurs during frame transmission, the Ethernet controller will continue the transmission for
at least 32 bit times, transmitting a JAM pattern consisting of 32 ones. If the collision occurs during the
preamble sequence, the JAM pattern will be sent after the end of the preamble sequence.
If a collision occurs within 512 bit times, the retry process is initiated. The transmitter waits a random
number of slot times. A slot time is 512 bit times. If a collision occurs after 512 bit times, then no
retransmission is performed and the EIR[LC] bit is set.
30.4.11 Internal and External Loopback
Both internal and external loopback are supported by the Ethernet controller. In loopback mode, both of
the FIFOs are used and the FEC actually operates in a full-duplex fashion. Both internal and external
loopback are configured using combinations of the LOOP and DRT bits in the RCR register and the FDEN
bit in the TCR register.
For both internal and external loopback set FDEN = 1.
For internal loopback set RCR[LOOP] = 1 and RCR[DRT] = 0. ETXEN and ETXER will not assert during
internal loopback. During internal loopback, the transmit/receive data rate is higher than in normal
operation because the internal system clock is used by the transmit and receive blocks instead of the clocks
from the external transceiver. This will cause an increase in the required system bus bandwidth for transmit
and receive data being DMA’d to/from external memory. It may be necessary to pace the frames on the
Table 30-51. Transmit Pause Frame Registers
PAUSE Frame Fields FEC Register Register Contents
48-bit destination address Internal 0x0180_C200_0001
48-bit Source Address {PALR[31:0], PAHR[31:16]} Physical Address
16-bit type PAHR[15:0] 0x8808
16-bit opcode OPD[31:16] 0x0001
16-bit PAUSE duration OPD[15:0] 0x0000 to 0xFFFF