14 mii management frame structure, Mii management frame structure -56 – Freescale Semiconductor MCF5480 User Manual
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MCF548x Reference Manual, Rev. 3
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Freescale Semiconductor
The data portion of the frame consists of N octets which corresponds to 2N nibbles being transmitted. The
order of each nibble is defined in the figure below.
Figure 30-42. MII Nibble/Octet to Octet/Nibble Mapping
The End-of-Frame delimiter is indicated by the de-assertion of the ETXEN signal for data on ETXD. For
data on ERXD, the de-assertion of ERXDV constitutes an End-of-Frame delimiter.
30.4.14 MII Management Frame Structure
A transceiver management frame being transmitted on the MII management interface uses the EMDIO and
EMDC signals. A transaction or frame on this serial interface has the following format:
<preamble><st><op><phyad><regad><ta><data><idle>
The (optional) preamble consists of a sequence of 32 continuous logic 1’s.
The start of frame (st), is indicated by a <01> pattern.
The operation code (op) for a read instruction is <10>. For a write operation, the operation code is <01>.
The physical address (phyad) is a five bit field which allows for up to 32 PHYs to be addressed. The first
address bit transmitted is the MSB of the address.
The register address (regad) is a five bit field which allows for 32 registers to be addressed within the each
PHY. The first register bit transmitted is the MSB of the address.
The turnaround (ta) field is a two bit field which provides spacing between the register address field and
the data field to avoid contention on the EMDIO signal during a read operation.
The data field is 16 bits wide. The first data bit transmitted and received is data bit 15.
During idle condition, EMDIO is in the high impedance state.
The MII management register set located in the PHY may consist of a basic register set and an extended
register set as defined below.
Table 30-52. MII Management Register Set
Register Addr.
Register Name
Basic/Extended
0
Control
B
1
Status
B
2,3
PHY Identifier
E
D0
D1
D2
D3
D4
D5
D6
D7
LSB
MSB
First Nibble
Second Nibble
D0
D1
D2
D3
LSB
MSB
First Bit
MII Nibble