Freescale Semiconductor MCF5480 - Manual (Page 99)

MCF548x External Signals
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 2-29
2.2.14 Timer Module Signals
The signals in the following sections are external interfaces to the four general-purpose MCF548x timers.
These 32-bit timers can capture timer values, trigger external events or internal interrupts, or count
external events.
2.2.14.1 Timer Inputs (TIN[3:0])
TINn can be programmed as clocks that cause events in the counter and prescalers. They can also cause
captures on the rising edge, falling edge, or both edges.
2.2.14.2 Timer Outputs (TOUT[3:0])
The programmable timer outputs, TOUTn, pulse or toggle on various timer events.
2.2.15 Debug Support Signals
The MCF548x complies with the IEEE 1149.1a JTAG testing standard. JTAG test pins are multiplexed
with background debug pins. Except for TCK, these signals are selected by the value of MTMOD0. If
MTMOD0 is high, JTAG signals are chosen; if it is low, debug module signals are chosen. MTMOD0
should be changed only while RSTI is asserted.
2.2.15.1 Processor Clock Output (PSTCLK)
The internal PLL generates this output signal, and is the processor clock output that is used as the timing
reference for the debug bus timing (PSTDDATA[7:0]). PSTCLK is at the same frequency as the internal
XLB and SDRAM bus frequency. The frequency is one-half the core frequency.
2.2.15.2 Processor Status Debug Data (PSTDDATA[7:0])
Processor status data outputs indicate both processor status and captured address/data values. They operate
at half the processor’s frequency, using PSTCLK. Given that real-time trace information appears as a
sequence of 4-bit data values, there are no alignment restrictions; that is, PST values and operands may
appear on either PSTDDATA[7:0] nibble. The upper nibble, PSTDDATA[7:4], is most significant.
2.2.15.3 Development Serial Clock/Test Reset (DSCLK/TRST)
If MTMOD0 is low, DSCLK is selected. DSCLK is the development serial clock for the serial interface to
the debug module. The maximum DSCLK frequency is 1/5 CLKIN.
If MTMOD0 is high, TRST is selected. TRST asynchronously resets the internal JTAG controller to the
test logic reset state, causing the JTAG instruction register to choose the bypass instruction. When this
occurs, JTAG logic is benign and does not interfere with normal MCF548x functionality.
Although TRST is asynchronous, Freescale recommends that it makes an asserted-to-negated transition
only while TMS is held high. TRST has an internal pull-up resistor so if it is not driven low, it defaults to
a logic level of 1. If TRST is not used, it can be tied to ground or, if TCK is clocked, to EV
DD
. Tying TRST
to ground places the JTAG controller in test logic reset state immediately. Tying it to EV
DD
causes the
JTAG controller (if TMS is a logic level of 1) to eventually enter test logic reset state after 5 TCK clocks.