Freescale Semiconductor MCF5480 - Manual (Page 109)

Features
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 3-5
ColdFire microprocessor family. The MAC features a four-stage execution pipeline, optimized for 32 × 32
multiplies. It is tightly coupled to the OEP, which can issue a 32 x 32 multiply with a 32-bit accumulation
and fetch a 32-bit operand in a single cycle. A 32 x 32 multiply with a 32-bit accumulation requires four
cycles before the next instruction can be issued.
Figure 3-2 shows basic functionality of the EMAC. A full set of instructions are provided for signed and
unsigned integers plus signed, fixed-point fractional input operands.
Figure 3-2. ColdFire Multiply-Accumulate Functionality Diagram
The EMAC provides functionality in the following three related areas, which are described in detail in
Chapter 4, “Enhanced Multiply-Accumulate Unit (EMAC) :”
• Signed and unsigned integer multiplies
• Multiply-accumulate operations with signed and unsigned fractional operands
• Miscellaneous register operations
3.2.1.2.3 Memory Management Unit (MMU)
The ColdFire memory management architecture provides a demand-paged, virtual-address environment
with hardware address translation acceleration. It supports supervisor/user, read, write, and execute
permission checking on a per-memory request basis.
The architecture defines the MMU TLB, associated control logic, TLB hit/miss logic, address translation
based on the TLB contents, and access faults due to TLB misses and access violations. It intentionally
leaves some virtual environment details undefined to maximize the software-defined flexibility. These
include the exact structure of the memory-resident pointer descriptor/page descriptor tables, the base
registers for these tables, the exact information stored in the tables, the methodology (if any) for
maintenance of access, and written information on a per-page basis.
3.2.1.2.4 Floating Point Unit (FPU)
The floating-point unit (FPU) provides hardware support for floating point math operations. The FPU
conforms to the American National Standards Institute (ANSI)/Institute of Electrical and Electronics
Engineers (IEEE) Standard for Binary Floating-Point Arithmetic (ANSI/IEEE Standard 754).
X
+/-
Operand Y Operand X
Shift 0,1,-1
Accumulator