Freescale Semiconductor MCF5480 - Manual (Page 126)

MCF548x Reference Manual, Rev. 3
3-22 Freescale Semiconductor
3.6.2 Instruction Set Summary
Table 3-8 lists user-mode instructions by opcode.
Save Internal Floating Point State fsave <ea>x Yes
Floating-Point Square Root fsqrt.{b,w,l,s,d} <ea>y FPx Yes
Floating-Point Subtract fsub.{b,w,l,s,d} <ea>y FPx Yes
Test Floating-Point Operand ftst.{b,w,l,s,d} <ea>y Yes
1
Operand sizes in this column reflect only newly supported operand sizes for existing instructions (Bcc, BRA,
BSR, CMP, CMPA, CMPI, and MOVE)
Table 3-8. User-Mode Instruction Set Summary
Instruction Operand Syntax Operand Size Operation
ADD
ADDA
Dy,<ea>x
<ea>y,Dx
<ea>y,Ax L
L
L Source + Destination
→ Destination
ADDI
ADDQ
#<data>,Dx
#<data>,<ea>x
L
L Immediate Data + Destination
→ Destination
ADDX Dy,Dx L Source + Destination + CCR[X]
→ Destination
AND <ea>y,Dx
Dy,<ea>x L
L Source
& Destination → Destination
ANDI #<data>, Dx L Immediate Data
& Destination → Destination
ASL Dy,Dx
#<data>,Dx
L
L CCR[X,C]
← (Dx << Dy) ← 0
CCR[X,C]
← (Dx << #<data>) ← 0
ASR Dy,Dx
#<data>,Dx
L
L msb
→ (Dx >> Dy) → CCR[X,C]
msb
→ (Dx >> #<data>) → CCR[X,C
Bcc <label> B, W, L If Condition True, Then PC + d
n
→ PC
BCHG Dy,<ea>x
#<data>,<ea>x
B, L
B, L ~ (<bit number> of Destination)
→ CCR[Z] →
<bit number> of Destination
BCLR Dy,<ea>x
#<data>,<ea>x
B, L
B, L ~ (<bit number> of Destination)
→ CCR[Z];
0
→<bit number> of Destination
BRA <label> B, W, L PC + d
n
→ PC
BSET Dy,<ea>x
#<data>,<ea>x
B, L
B, L ~ (<bit number> of Destination)
→ CCR[Z];
1
→ <bit number> of Destination
BSR <label> B, W, L SP – 4
→ SP; nextPC → (SP); PC + d
n
→ PC
BTST Dy,<ea>x
#<data>,<ea>x
B, L
B, L ~ (<bit number> of Destination)
→ CCR[Z]
CLR <ea>x B, W, L 0
→ Destination
Table 3-7. V4 New Instruction Summary (Continued)
Instruction Mnemonic
1
Source Destination M68000