1 move instruction execution timing, Move instruction execution timing -28 – Freescale Semiconductor MCF5480 User Manual

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MCF548x Reference Manual, Rev. 3

3-28

Freescale Semiconductor

The OEP can complete all memory accesses without memory causing any stalls. Thus, these

timings assume an infinite, zero-wait state memory attached to the core.

Operand accesses are assumed to be aligned as follows:
— 16-bit operands are aligned on 0-modulo-2 addresses
— 32-bit operands are aligned on 0-modulo-4 addresses
Operands that do not meet these guidelines are misaligned.

Table 3-10

shows how the core

decomposes a misaligned operand reference into a series of aligned accesses.

3.7.1

MOVE Instruction Execution Timing

The following tables show execution times for the MOVE.{B,W,L} instructions.

Table 3-13

shows the

timing for the other generic move operations.

NOTE

In these tables, times using PC-relative effective addressing modes are the

same as using An-relative mode.

The (xxx).wl nomenclature refers to both forms of absolute addressing,

(xxx).w and (xxx).l.

Table 3-11

lists execution times for MOVE.{B,W} instructions.

Table 3-10. Misaligned Operand References

A[1:0]

Size

Bus Operations

Additional C(R/W)

1

1

Each timing entry is presented as C(r/w), described as follows:

C is the number of processor clock cycles, including all applicable operand fetches and writes, as well as all
internal core cycles required to complete the instruction execution.

r/w is the number of operand reads (r) and writes (w) required by the instruction. An operation performing a
read-modify write function is denoted as (1/1).

x1

Word

Byte, Byte

2(1/0) if read
1(0/1) if write

x1

Long

Byte, Word, Byte

3(2/0) if read
2(0/2) if write

10

Long

Word, Word

2(1/0) if read
1(0/1) if write

ET with {<ea> = (d16,PC)}

equals ET with {<ea> = (d16,An)}

ET with {<ea> = (d8,PC,Xi*SF)}

equals ET with {<ea> = (d8,An,Xi*SF)}

Table 3-11. Move Byte and Word Execution Times

Source

Destination

Rx

(Ax)

(Ax)+

–(Ax)

(d16,Ax)

(d8,Ax,Xi*SF) (xxx).wl

Dy

1(0/0)

1(0/1)

1(0/1)

1(0/1)

1(0/1)

2(0/1)

1(0/1)

Ay

1(0/0)

1(0/1)

1(0/1)

1(0/1)

1(0/1)

2(0/1)

1(0/1)

(Ay)

1(1/0)

2(1/1)

2(1/1)

2(1/1)

2(1/1)

3(1/1)

2(1/1)

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