Freescale Semiconductor MCF5480 - Manual (Page 137)

Instruction Execution Timing
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 3-33
3.7.5 Branch Instruction Execution Timing
Table 3-17 shows general branch instruction timing.
move.w SR,Dx 1(0/0) — — — — — — —
move.w <ea>,SR 4(0/0) — — — — — — 4(0/0)
movec Ry,Rc 20(0/1) — — — — — — —
movem.l 1 <ea>,&list — n(n/0) — — n(n/0) — — —
movem.l &list,<ea> — n(0/n) — — n(0/n) — — —
nop 6(0/0) — — — — — — —
pea <ea> — 1(0/1) — — 1(0/1) 2 2(0/1) 3 1(0/1) —
pulse 1(0/0) — — — — — — —
stop #imm — — — — — — — 6(0/0)
4
trap #imm — — — — — — — 18(1/2)
tpf 1(0/0) — — — — — — —
tpf.w 1(0/0) — — — — — — —
tpf.l 1(0/0) — — — — — — —
unlk Ax 1(1/0) — — — — — — —
wddata.l <ea> — 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 1(1/0) —
wdebug.l <ea> — 3(2/0) — — 3(2/0) — — —
1
n is the number of registers moved by the MOVEM opcode.
2 PEA execution times are the same for (d16,PC).
3 PEA execution times are the same for (d8,PC,Xi*SF).
4
The execution time for STOP is the time required until the processor begins sampling continuously for interrupts.
Table 3-17. General Branch Instruction Execution Times
Opcode <ea>
Effective Address
Rn (An) (An)+ –(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx>
bra — — — — 1(0/1)
1
1
Assumes branch acceleration. Depending on the pipeline status, execution times may vary from 1 to 3 cycles.
— — —
bsr — — — — 1(0/1)
1
— — —
jmp <ea> — 5(0/0) — — 5(0/0) 1 6(0/0) 1(0/0) 1 —
jsr <ea> — 5(0/1) — — 5(0/1) 6(0/1) 1(0/1)
1
—
rte — — 15(2/0) — — — — —
rts — — 2(1/0) 2
9(1/0)
3
8(1/0)
4
— — — — —
Table 3-16. Miscellaneous Instruction Execution Times (Continued)
Opcode <ea>
Effective Address
Rn (An) (An)+ –(An) (d16,An) (d8,An,Xi*SF) (xxx).wl #<xxx>