Freescale Semiconductor MCF5480 - Manual (Page 168)

MCF548x Reference Manual, Rev. 3
5-2 Freescale Semiconductor
• The address access control logic, address attribute logic, memories, and controller function as in
previous ColdFire versions with the addition of the MMU. The MMU, its TLB, and associated
control reside in the logic.
• The MMU appears as a memory-mapped device in the space. Information for access error fault
processing is stored in the MMU.
• A precise fault (transfer error acknowledge) signals the core on translation (TLB miss) and access
faults. The core supports an instruction restart model for this fault class. Note that this structure
uses the existing ColdFire access error fault vector and needs no new ColdFire exception stack
frames.
• The following additions are made to the memory access control to better support the fault
processing and memory maintenance necessary for this virtual addressing environment. These
additions improve memory performance and functionality for physical and virtual address
environments:
— New supervisor-protect bits to the access control registers (ACRs) and the cache control
register (CACR)
— Improved addressing of the ACRs
5.2.2 MMU Architecture Location
Figure 5-1 shows the placement of the MMU/TLB hardware. It follows a traditional model in which it is
closely coupled to the processor local-memory controllers.