Freescale Semiconductor MCF5480 - Manual (Page 173)

Debugging in a Virtual Environment
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 5-7
5.2.3.11 Supervisor Protection
Each instruction or data reference is either a supervisor or user access. The CPU’s status register supervisor
bit (SR[S]) determines the operating mode. New ACR and CACR bits protect supervisor space. See
Table 5-1 .
5.3 Debugging in a Virtual Environment
To support debugging in a virtual environment, numerous enhancements are implemented in the ColdFire
debug architecture. These enhancements are collectively called Debug revision D and primarily relate to
the addition of an 8-bit address space identifier (ASID) to yield a 40-bit virtual address. This expansion
affects two major debug functions:
• The ASID is optionally included in the hardware breakpoint registers specification. For example,
the four PC breakpoint registers are expanded by 8 bits each, so that a specific ASID value can be
part of the breakpoint instruction address. Likewise, data address/data breakpoint registers are
expanded to include an ASID value. The new control registers define whether and how the ASID
is included in the breakpoint comparison trigger logic.
• The debug module implements the concept of ownership trace in which an ASID value can be
optionally displayed as part of real-time trace. When enabled, real-time trace displays instruction
addresses on any change-of-flow instruction that is not absolute or PC-relative. For Debug revision
D architecture, the address display is expanded to optionally include ASID contents, thus providing
the complete instruction virtual address on these instructions. Additionally, when a Sync_PC serial
BDM command is loaded from the external development system, the processor displays the
complete virtual instruction address, including the 8-bit ASID value.
The MMU control registers are accessible through serial BDM commands. See Chapter 8, “Debug
Support.”
5.4 Virtual Memory Architecture Processor Support
To support the MMU, enhancements have been made to the exception model, the stack pointers, and the
access error stack frame.
5.4.1 Precise Faults
To support demand-paging, all memory references require precise, recoverable faults. The ColdFire
instruction restart mechanism ensures that a faulted instruction restarts from the beginning of execution;
that is, no internal state information is saved when an exception occurs and none is restored when the
handler ends. Given the PC address defined in the exception stack frame, the processor reestablishes
program execution by transferring control to the given location as part of the RTE (return from exception)
instruction.
For a detailed description, see
Section 3.9, “Precise Faults.”
5.4.2 Supervisor/User Stack Pointers
To provide the required isolation between these operating modes as dictated by a virtual memory
management scheme, a user stack pointer (A7–USP) is added. The appropriate stack pointer register (SSP,
USP) is accessed as a function of the processor’s operating mode.