Freescale Semiconductor MCF5480 - Manual (Page 251)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 8-1
Chapter 8
Debug Support
8.1 Introduction
This chapter describes the Revision D enhanced hardware debug support in the ColdFire Version 4. This
revision of the ColdFire debug architecture encompasses earlier revisions. An expanded set of debug
functionality is defined as Revision B (or Rev. B). The further enhanced debug architecture implemented
in the Version 4 ColdFire is known as Revision C (or Rev. C). The addition of the memory management
unit (MMU) in the Version 4e ColdFire requires corresponding enhancements to the ColdFire debug
functionality, resulting in Revision D.
8.1.1 Overview
The debug module interface is shown in Figure 8-1 .
Figure 8-1. Processor/Debug Module Interface
Debug support is divided into three areas:
• Real-time trace support: The ability to determine the dynamic execution path through an
application is fundamental for debugging. The ColdFire solution implements an 8-bit parallel
output bus that reports processor execution status and data to an external BDM emulator system.
See Section 8.3, “Real-Time Trace Support .”
• Background debug mode (BDM): Provides low-level debugging in the ColdFire processor
complex. In BDM, the processor complex is halted and a variety of commands can be sent to the
processor to access memory and registers. The external BDM emulator uses a three-pin, serial,
full-duplex channel. See Section 8.5, “Background Debug Mode (BDM) ,” and Section 8.4,
“Memory Map/Register Definition .”
• Real-time debug support: BDM requires the processor to be halted, which many real-time
embedded applications cannot do. Debug interrupts let real-time systems execute a unique service
routine that can quickly save key register and variable contents and return the system to normal
operation without halting. External development systems can access saved data, because the
hardware supports concurrent operation of the processor and BDM-initiated commands. In
addition, the option is provided to allow interrupts to occur. See Section 8.6, “Real-Time Debug
Support .”
The Version 2 ColdFire core implemented the original debug architecture, now called Revision A. Based
on feedback from customers and third-party developers, enhancements have been added to succeeding
ColdFire CPU Core
Debug Module
High-speed
Communication Port
DSCLK, DSI, DSO
Control
BKPT
local bus
Trace Port
PSTDDATA[7:0]
PSTCLK