Freescale Semiconductor MCF5480 - Manual (Page 255)

Real-Time Trace Support
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 8-5
NOTE
A PST marker and its data display are sent contiguously. Except for this
transmission, the IDLE status (0x0) can appear anytime. Again, given that
real-time trace information appears as a sequence of 4-bit values, there are
no alignment restrictions. That is, PST values and operands may appear on
either nibble of PSTDDATA.
8.3 Real-Time Trace Support
Real-time trace, which defines the dynamic execution path, is a fundamental debug function. The ColdFire
solution is to include a parallel output port providing encoded processor status and data to an external
development system. This 8-bit port is partitioned into two consecutive 4-bit nibbles. Each nibble can
either transmit information concerning the processor’s execution status (PST) or debug data (DDATA).
The processor status may not be related to the current bus transfer, due to the decoupling FIFOs.
External development systems can use PSTDDATA outputs with an external image of the program to
completely track the dynamic execution path. This tracking is complicated by any change in flow,
especially when branch target address calculation is based on the contents of a program-visible register
(variant addressing). PSTDDATA outputs can be configured to display the target address of such
instructions in sequential nibble increments across multiple processor clock cycles, as described in
Section 8.3.1, “Begin Execution of Taken Branch (PST = 0x5) .” Four 32-bit storage elements form a FIFO
buffer connecting the processor’s high-speed local bus to the external development system through
PSTDDATA[7:0]. The buffer captures branch target addresses and certain data values for eventual display
on the PSTDDATA port, two nibbles at a time starting with the least significant bit (lsb).
Execution speed is affected only when three storage elements contain valid data to be dumped to the
PSTDDATA port. This occurs only when two values are captured simultaneously in a read-modify-write
operation. The core stalls until two FIFO entries are available.
Table 8-4 shows the encoding of these signals.
Table 8-4. Processor Status Encoding
PST[3:0]
Definition
Hex Binary
0x0 0000 Continue execution. Many instructions execute in one processor cycle. If an instruction requires
more clock cycles, subsequent clock cycles are indicated by driving PSTDDATA outputs with this
encoding.
0x1 0001 Begin execution of one instruction. For most instructions, this encoding signals the first clock cycle
of an instruction’s execution. Certain change-of-flow opcodes, plus the PULSE and WDDATA
instructions, generate different encodings.
0x2 0010 Begin execution of two instructions. For superscalar instruction dispatches, this encoding signals the
first clock cycle of the simultaneous instructions’ execution.
0x3 0011 Entry into user-mode. Signaled after execution of the instruction that caused the ColdFire processor
to enter user mode. If the display of the ASID is enabled (CSR[3] = 1), the following occurs:
• The 8-bit ASID follows the instruction address; that is, the PSTDDATA sequence is {0x3, 0x5,
marker, instruction address, 0x8, ASID}, where 0x8 is the ASID data marker.
• Whenever the current ASID is loaded by the privileged MOVEC instruction, the ASID is displayed
on PSTDDATA. The resulting PSTDDATA sequence for the MOVEC instruction is then {0x1, 0x8,
ASID}, where the 0x8 is the data marker for the ASID.