Freescale Semiconductor MCF5480 - Manual (Page 256)

MCF548x Reference Manual, Rev. 3
8-6 Freescale Semiconductor
8.3.1 Begin Execution of Taken Branch (PST = 0x5)
PST is 0x5 when a taken branch is executed. For some opcodes, a branch target address may be displayed
on PSTDDATA depending on the CSR settings. CSR also controls the number of address bytes displayed,
which is indicated by the PST marker value immediately preceding the PSTDDATA nibble that begins the
data output.
Multiple byte DDATA values are displayed in least-to-most-significant order. The processor captures only
those target addresses associated with taken branches which use a variant addressing mode, that is, RTE
and RTS instructions, JMP and JSR instructions using address register indirect or indexed addressing
modes, and all exception vectors.
0x4 0100 Begin execution of PULSE and WDDATA instructions. PULSE defines logic analyzer triggers for
debug or performance analysis. WDDATA lets the core write any operand (byte, word, or longword)
directly to the PSTDDATA port, independent of debug module configuration. When WDDATA is
executed, a value of 0x4 is signaled, followed by the appropriate marker, and then the data transfer
on the PSTDDATA port. Transfer length depends on the WDDATA operand size.
0x5 0101 Begin execution of taken branch or SYNC_PC command. For some opcodes, a branch target
address may be displayed on PSTDDATA depending on the CSR settings. CSR also controls the
number of address bytes displayed, indicated by the PST marker value preceding the DDATA nibble
that begins the data output. See
Section 8.3.1, “Begin Execution of Taken Branch (PST = 0x5) .” Also
indicates that the SYNC_PC command has been issued.
0x6 0110 Begin execution of instruction plus a taken branch. The processor completes execution of a taken
conditional branch instruction and simultaneously starts executing the target instruction. This is
achieved through branch folding.
0x7 0111 Begin execution of return from exception (RTE) instruction.
0x8–0xB 1000–1011 Indicates the number of bytes to be displayed on the DDATA port on subsequent clock cycles. The
value is driven onto the PSTDDATA port one cycle before the data is displayed.
0x8 Begin 1-byte transfer on PSTDDATA.
0x9 Begin 2-byte transfer on PSTDDATA.
0xA Begin 3-byte transfer on PSTDDATA.
0xB Begin 4-byte transfer on PSTDDATA.
0xC 1100 Normal exception processing. Exceptions that enter emulation mode (debug interrupt or optionally
trace) generate a different encoding, as described below. Because the 0xC encoding defines a
multiple-cycle mode, PSTDDATA outputs are driven with 0xC until exception processing completes.
0xD 1101 Emulator mode exception processing. Displayed during emulation mode (debug interrupt or
optionally trace). Because this encoding defines a multiple-cycle mode, PSTDDATA outputs are
driven with 0xD until exception processing completes.
0xE 1110 A breakpoint state change causes this encoding to assert for one cycle only followed by the trigger
status value. If the processor stops waiting for an interrupt, the encoding is asserted for multiple
cycles. See
Section 8.3.2, “Processor Stopped or Breakpoint State Change (PST = 0xE) .”
0xF 1111 Processor is halted. Because this encoding defines a multiple-cycle mode, the PSTDDATA outputs
display 0xF until the processor is restarted or reset. (see
Section 8.5.1, “CPU Halt ”)
Table 8-4. Processor Status Encoding (Continued)
PST[3:0]
Definition
Hex Binary