Freescale Semiconductor MCF5480 - Manual (Page 257)

Real-Time Trace Support
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 8-7
The simplest example of a branch instruction using a variant address is the compiled code for a C language
case statement. Typically, the evaluation of this statement uses the variable of an expression as an index
into a table of offsets, where each offset points to a unique case within the structure. For such
change-of-flow operations, the V4 microarchitecture uses the debug pins to output the following sequence
of information on two successive processor clock cycles:
1. Use PSTDDATA (0x5) to identify that a taken branch is executed.
2. Optionally signal the target address to be displayed sequentially on the PSTDDATA pins.
Encodings 0x9–0xB identify the number of bytes displayed.
3. The new target address is optionally available on subsequent cycles using the PSTDDATA port.
The number of bytes of the target address displayed on this port is configurable (2, 3, or 4 bytes,
where the encoding is 0x9, 0xA, and 0xB, respectively).
Another example of a variant branch instruction would be a JMP (A0) instruction. Figure 8-4 shows when
the PSTDDATA outputs that indicate when a JMP (A0) executed, assuming the CSR was programmed to
display the lower 2 bytes of an address.
Figure 8-4. Example JMP Instruction Output on PSTDDATA
PSTDDATA is driven two nibbles at a time with a 0x59; 0x5 indicates a taken branch and the marker value
0x9 indicates a 2-byte address. Thus, the subsequent 4 nibbles display the lower 2 bytes of address register
A0 in least-to-most-significant nibble order. The PSTDDATA output after the JMP instruction continues
with the next instruction.
8.3.2 Processor Stopped or Breakpoint State Change (PST = 0xE)
The 0xE encoding is generated either as a one- or multiple-cycle issue as follows:
• When the core is stopped by a STOP instruction, this encoding appears in multiple-cycle format.
The ColdFire processor remains stopped until an interrupt occurs; thus, PSTDDATA outputs
display 0xE until stopped mode is exited.
• When a breakpoint status change is to be output on PSTDDATA, 0xE is displayed for one cycle,
followed immediately with the 4-bit value of the current trigger status, where the trigger status is
left justified rather than in the CSR[BSTAT] description. Section 8.4.2, “Configuration/Status
Register (CSR) ,” shows that status is right justified. That is, the displayed trigger status on
PSTDDATA after a single 0xE is as follows:
— 0x0 = no breakpoints enabled
— 0x2 = waiting for level-1 breakpoint
— 0x4 = level-1 breakpoint triggered
— 0xA = waiting for level-2 breakpoint
— 0xC = level-2 breakpoint triggered
Thus, 0xE can indicate multiple events, based on the next value, as Table 8-5 shows.
PSTDDATA
PSTCLK
0x59 A0[3–0,7–4] A0[11–8,15–12]
Processor Clock