Freescale Semiconductor MCF5480 - Manual (Page 301)

Real-Time Debug Support
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 8-51
Figure 8-50. WDMREG Command Sequence
Operand Data: Longword data is written into the specified debug register. The data is supplied
most-significant word first.
Result Data: Command complete status (0xFFFF) is returned when register write is complete.
8.6 Real-Time Debug Support
The ColdFire Family provides support debugging real-time applications. For these types of embedded
systems, the processor must continue to operate during debug. The foundation of this area of debug support
is that while the processor cannot be halted to allow debugging, the system can generally tolerate the small
intrusions of the BDM inserting instructions into the pipeline with minimal effect on real-time operation.
The debug module provides three types of breakpoints: PC with mask, operand address range, and data
with mask. These breakpoints can be configured into one- or two-level triggers with the exact trigger
response also programmable. The debug module programming model can be written from either the
external development system using the debug serial interface or from the processor’s supervisor
programming model using the WDEBUG instruction. Only CSR is readable using the external
development system.
8.6.1 Theory of Operation
Breakpoint hardware can be configured through TDR[TCR] to respond to triggers by displaying
PSTDDATA, initiating a processor halt, or generating a debug interrupt. As shown in Table 8-28 , when a
breakpoint is triggered, an indication (CSR[BSTAT]) is provided on the PSTDDATA output port of the
DDATA information when it is not displaying captured processor status, operands, or branch addresses.
See Section 8.3.2, “Processor Stopped or Breakpoint State Change (PST = 0xE) .”
The breakpoint status is also posted in CSR. Note that CSR[BSTAT] is cleared by a CSR read when either
a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and a level-2 breakpoint is not enabled.
Status is also cleared by writing to either TDR or XTDR to disable trigger options.
Table 8-28. PSTDDATA Nibble/CSR[BSTAT] Breakpoint Response
PSTDDATA Nibble/CSR[BSTAT]
1
1
Encodings not shown are reserved for future use.
Breakpoint Status
0000/0000 No breakpoints enabled
0010/0001 Waiting for level-1 breakpoint
0100/0010 Level-1 breakpoint triggered
1010/0101 Waiting for level-2 breakpoint
1100/0110 Level-2 breakpoint triggered
WDMREG
???
MS DATA
’NOT READY’
LS DATA
’NOT READY’
XXX
’ILLEGAL’
NEXT CMD
’NOT READY’
NEXT CMD
’CMD COMPLETE’