2 mmu functionality, 3 mmu organization, 1 mmu base address register (mmubar) – Freescale Semiconductor MCF5480 User Manual
Page 176: Mmu functionality -10, Mmu organization -10, Mmu base address register (mmubar) -10
MCF548x Reference Manual, Rev. 3
5-10
Freescale Semiconductor
•
If virtual mode is enabled, any normal mode access that does not hit in the MMUBAR,
RAMBARs, ROMBARs, or ACRs is considered a normal mode virtual address request and
generates its access attributes from the MMU. For this case, the default CACR address attributes
are not used.
The MMU also uses TLB contents to perform virtual-to-physical address translation.
5.5.2
MMU Functionality
The MMU provides virtual-to-physical address translation and memory access control. The MMU consists
of memory-mapped, control, status, and fault registers, and a TLB that can be accessed through MMU
registers. Supervisor software can access these resources through MMUBAR. Software can control
address translation and access attributes of a virtual address by configuring MMU control registers and
loading the MMU’s TLB, which functions as a cache, associating virtual addresses to corresponding
physical addresses and providing access attributes. Each TLB entry maps a virtual page. Several page sizes
are supported. Features such as clear-all and probe-for-hit help maintain TLBs.
Fault-free, virtual address accesses that hit in the TLB incur no pipeline delay. Accesses that miss the TLB
or hit the TLB but violate an access attribute generate an access error exception. On an access error,
software can reference address and information registers in the MMU to retrieve data. Depending on the
fault source, software can obtain and load a new TLB entry, modify the attributes of an existing entry, or
abort the faulting process.
5.5.3
MMU Organization
Access to the MMU memory-mapped region is controlled by MMUBAR, a 32-bit supervisor control
register at 0x008 that is accessed using MOVEC or the serial BDM debug port. The ColdFire
Programmers Reference Manual describes the MOVEC instruction.
5.5.3.1
MMU Base Address Register (MMUBAR)
shows MMUBAR. The default reset state is an invalid MMUBAR, so that the MMU is disabled
and the memory-mapped space is not visible.
describes MMU base address register fields.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
BA
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
V
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
CPU + 0x008
Figure 5-3. MMU Base Address Register (MMUBAR)