3 floating-point status register (fpsr), Floating-point status register (fpsr) -9 – Freescale Semiconductor MCF5480 User Manual
Page 199
Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor
6-9
6.3.3
Floating-Point Status Register (FPSR)
, contains a floating-point condition code byte (FPCC), a floating-point exception
status byte (EXC), and a floating-point accrued exception byte (AEXC). The user can read or write all
FPSR bits. Execution of most floating-point instructions modifies FPSR. FPSR is loaded using FMOVE
or FRESTORE. A processor reset or a restore operation of the null state clears the FPSR.
The floating-point condition code byte contains 4 condition code bits that are set after completion of all
arithmetic instructions involving the floating-point data registers. The floating-point store operation,
FMOVEM, and move system control register instructions do not affect the FPCC.
The exception status byte contains a bit for each floating-point exception that might have occurred during
the most recent arithmetic instruction or move operation. This byte is cleared at the start of all operations
that generate floating-point exceptions (except FBcc only affects BSUN and that only for nonaware tests).
Operations that do not generate floating-point exceptions do not clear this byte. An exception handler can
use this byte to determine which floating-point exception or exceptions caused a trap. The equations below
the table show the comparative relationship between the EXC byte and AEXC byte.
The accrued exception byte contains 5 required bits for IEEE-754 exception-disabled operations. These
exceptions are logical combinations of EXC bits. AEXC records all floating-point exceptions since AEXC
was last cleared, either by writing to FPSR or as a result of reset or a restore operation of the null state.
Many users disable traps for some or all floating-point exception classes. AEXC eliminates the need to
poll EXC after each floating-point instruction. At the end of arithmetic operations, EXC bits are logically
combined to form an AEXC value that is logically ORed into the existing AEXC byte (FBcc only updates
IOP). This operation creates sticky floating-point exception bits in AEXC that the user can poll only at the
end of a series of floating-point operations. A sticky bit is one that remains set until the user clears it.
Setting or clearing AEXC bits neither causes nor prevents an exception. The equations below the table
show relationships between EXC and AEXC. Comparing the current value of an AEXC bit with a
combination of EXC bits derives a new value in the corresponding AEXC bit. These boolean equations
apply to setting AEXC bits at the end of each operation affecting AEXC.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Floating-Point Condition Code Byte (FPCC)
R
0
0
0
0
N
Z
I
NAN
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Exception Status Byte (EXC)
Floating-Point Accrued Exception Byte (AEXC)
R BSUN INAN OPERR OVFL UNFL DZ INEX IDE
IOP
OVFL UNFL
DZ
INEX
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reg
Addr
CPU + 0x822
Figure 6-10. Floating-Point Status Register (FPSR)