Freescale Semiconductor MCF5480 - Manual (Page 201)

Floating-Point Computational Accuracy
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 6-11
For FPU instructions that can generate exception traps, the 32-bit FPIAR is loaded with the instruction PC
address before the FPU begins execution. In case of an FPU exception, the trap handler can use the FPIAR
contents to determine the instruction that generated the exception. FMOVE to/from FPCR, FPSR, or
FPIAR and FMOVEM instructions cannot generate floating-point exceptions; therefore, they do not
modify FPIAR. A reset or a null-restore operation clears FPIAR.
6.4 Floating-Point Computational Accuracy
The FPU performs all floating-point internal operations in double-precision. It supports mixed-mode
arithmetic by converting single-precision operands to double-precision values before performing the
specified operation. The FPU converts all memory data formats to the double-precision data format and
stores the value in a floating-point register or uses it as the source operand for an arithmetic operation.
When moving a double-precision floating-point value from a floating-point data register, the FPU can
convert the data depending on the destination, as follows:
• Valid data formats for memory destination: B, W, L, S, or D
• Valid data formats for integer data register destinations: B, W, L, or S
Normally if the input operand is a denormalized number, the number must be normalized before an FPU
instruction can be executed. A denormalized input operand is converted to zero if the input denorm
exception (IDE) is disabled. If IDE is enabled, the floating-point engine traps to allow software action to
be taken by the handler.
6.4.1 Intermediate Result
All FPU calculations use an intermediate result. When the FPU performs any operation, the calculation is
carried out using double-precision inputs, and the intermediate result is calculated as if to produce infinite
precision. After the calculation is complete, any necessary rounding of the intermediate result for the
selected precision is performed and the result is stored in the destination.
Figure 6-11 shows the intermediate result format. The intermediate result’s exponent for some dyadic
operations (for example, multiply and divide) can easily overflow or underflow the 11-bit exponent of the
designated floating-point register. To simplify overflow and underflow detection, intermediate results in
the FPU maintain a 12-bit two’s complement, integer exponent. Detection of an intermediate result
overflow or underflow always converts the 12-bit exponent into a 11-bit biased exponent before being
stored in a floating-point data register. The FPU internally maintains a 56-bit mantissa for rounding
purposes. The mantissa is always rounded to 53 bits (or fewer, depending on the selected rounding
precision) before it is stored in a floating-point data register.
Figure 6-11. Intermediate Result Format
If the destination is a floating-point data register, the result is in double-precision format but may be
rounded to single-precision, if required by the rounding precision, before being stored. If the
single-precision mode is selected, the exponent value is in the correct range even if it is stored in
52-Bit Fraction
Integer lsb
Guard
Sticky
Round
12-Bit Exponent
56-Bit Intermediate Mantissa