Freescale Semiconductor MCF5480 - Manual (Page 202)

MCF548x Reference Manual, Rev. 3
6-12 Freescale Semiconductor
double-precision format. If the destination is a memory location or an integer data register, rounding
precision is ignored. In this case, a number in the double-precision format is taken from the source
floating-point data register, rounded to the destination format precision, and then written to memory or the
integer data register.
Depending on the selected rounding mode or destination data format, the location of the lsb of the mantissa
and the locations of the guard, round, and sticky bits in the 56-bit intermediate result mantissa vary. Guard
and round bits are calculated exactly. The sticky bit creates the illusion of an infinitely wide intermediate
result. As the arrow in Figure 6-11 shows, the sticky bit is the logical OR of all bits to the right of the round
bit in the infinitely precise result. During calculation, nonzero bits generated to the right of the round bit
set the sticky bit. Because of the sticky bit, the rounded intermediate result for all required IEEE arithmetic
operations in RN mode can err by no more than one half unit in the last place.
6.4.2 Rounding the Result
The FPU supports the four rounding modes specified by the IEEE-754 standard: round-to-nearest (RN),
round-toward-zero (RZ), round-toward-plus-infinity (RP), and round-toward-minus-infinity (RM). The
RM and RP modes are often referred to as directed-rounding-modes and are useful in interval arithmetic.
Rounding is accomplished through the intermediate result. Single-precision results are rounded to a 24-bit
mantissa boundary; double-precision results are rounded to a 53-bit mantissa boundary.
The current floating-point instruction can specify rounding precision, overriding the rounding precision
specified in FPCR for the duration of the current instruction. For example, the rounding precision for
FADD is determined by FPCR, while the rounding precision for FSADD is single-precision, independent
of FPCR.
Range control helps emulate devices that support only single-precision arithmetic by rounding the
intermediate result’s mantissa to the specified precision and checking that the intermediate exponent is in
the representable range of the selected rounding precision. If the intermediate result’s exponent exceeds
the range, the appropriate underflow or overflow value is stored as the result in the double-precision format
exponent. For example, if the data format and rounding mode is single-precision RM and the result of an
arithmetic operation overflows the single-precision format, the maximum normalized single-precision
value is stored as a double-precision number in the destination floating-point data register; that is, the
unbiased 11-bit exponent is 0x0FF and the 52-bit fraction is 0xF_FFFF_E000_0000. If an infinity is the
appropriate result for an underflow or overflow, the infinity value for the destination data format is stored
as the result; that is, the exponent has the maximum value and the mantissa is zero.
Figure 6-12 shows the algorithm for rounding an intermediate result to the selected rounding precision and
destination data format. If the destination is a floating-point register, the rounding boundary is determined
by either the selected rounding precision specified by FPCR[PREC] or by the instruction itself. For
example, FSADD and FDADD specify single- and double-precision rounding regardless of FPCR[PREC].
If the destination is memory or an integer data register, the destination data format determines the rounding
boundary. If the rounded result of an operation is inexact, INEX is set in FPSR[EXC].