Freescale Semiconductor MCF5480 - Manual (Page 204)

MCF548x Reference Manual, Rev. 3
6-14 Freescale Semiconductor
The lsb of the rounded result does not increment even though the guard bit is set in the intermediate result.
The IEEE-754 standard specifies this way of handling ties. If the destination data format is
double-precision and there is a difference between the infinitely precise intermediate result and the
round-to-nearest result, the relative difference is 2
–53
(the value of the guard bit). This error is equal to half
of the lsb’s value and is the worst case error that can be introduced with RN mode. Thus, the term one-half
unit in the last place correctly identifies the error bound for this operation. This error specification is the
relative error present in the result; the absolute error bound is equal to 2
exponent
x 2
–53
. Table 6-7 shows
the error bound for other rounding modes.
The difference between the infinitely precise result and the rounded result is 2
–53
+ 2
–54
+ 2
–55
, which is
slightly less than 2
–52
(the value of the lsb). Thus, the error bound for this operation is not more than one
unit in the last place. The FPU meets these error bounds for all arithmetic operations, providing accurate,
repeatable results.
6.5 Floating-Point Post-Processing
Most operations end with post-processing, for which the FPU provides two steps. First, FPSR[FPCC] bits
are set or cleared at the end of each arithmetic or move operation to a single floating-point data register.
FPCC bits are consistently set based on the result of the operation. Second, the FPU supports 32
conditional tests that allow floating-point conditional instructions to test floating-point conditions in the
same way that integer conditional instructions test the integer condition code. The combination of
consistently set FPCC bits and the simple programming of conditional instructions gives the processor a
highly flexible, efficient way to change program flow based on floating-point results. When the summary
for each instruction is read, it should be assumed that an instruction performs post processing, unless the
summary specifically states otherwise. The following paragraphs describe post processing in detail.
6.5.1 Underflow, Round, and Overflow
During calculation of an arithmetic result, the FPU has more precision and range than the 64-bit
double-precision format. However, the final result is a double-precision value. In some cases, an
intermediate result becomes either smaller or larger than can be represented in double-precision. Also, the
operation can generate a larger exponent or more bits of precision than can be represented in the chosen
rounding precision. For these reasons, every arithmetic instruction ends by checking for underflow,
rounding the result and checking for overflow.
At the completion of an arithmetic operation, the intermediate result is checked to see if it is too small to
be represented as a normalized number in the selected precision. If so, the underflow (UNFL) bit is set in
FPSR[EXC]. If no underflow occurs, the intermediate result is rounded according to the user-selected
Table 6-6. Tie-Case Example
Result Integer 52-Bit Fraction Guard Round Sticky
Intermediate x xxx…x00 1 0 0
Rounded-to-Nearest x xxx…x00 0 0 0
Table 6-7. Round Mode Error Bounds
Result Integer 52-Bit Fraction Guard Round Sticky
Intermediate x xxx…x00 1 1 1
Rounded-to-Zero x xxx…x00 0 0 0