2 input not-a-number (inan), 3 input denormalized number (ide), Input not-a-number (inan) -20 – Freescale Semiconductor MCF5480 User Manual

Page 210: Input denormalized number (ide) -20

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MCF548x Reference Manual, Rev. 3

6-20

Freescale Semiconductor

6.6.1.2

Input Not-A-Number (INAN)

The INAN exception is a mechanism for handling a user-defined, non-IEEE data type. If either input

operand is a NAN, FPSR[INAN] is set. By enabling this exception, the user can override the default action

taken for NAN operands. Because FMOVEM, FMOVE FPCR, and FSAVE instructions do not modify

status bits, they cannot generate exceptions. Therefore, these instructions are useful for manipulating

INANs. See

Table 6-13

.

6.6.1.3

Input Denormalized Number (IDE)

The input denorm bit, FPCR[IDE], provides software support for denormalized operands. When the IDE

exception is disabled, the operand is treated as zero, FPSR[INEX] is set, and the operation proceeds. When

the IDE exception is enabled and an operand is denormalized, an IDE exception is taken, but FPSR[INEX]

is not set to allow the handler to set it appropriately. See

Table 6-14

.

Note that the FPU never generates denormalized numbers. If necessary, software can create them in the

underflow exception handler.

Table 6-12. BSUN Exception Enabled/Disabled Results

Condition

BSUN

Description

Exception

disabled

0

The floating-point condition is evaluated as if it were the equivalent IEEE-aware conditional
predicate. No exceptions are taken.

Exception

Enabled

1

The processor takes a floating-point pre-instruction exception.
The BSUN exception is unique in that the exception is taken before the conditional
predicate is evaluated. If the user BSUN exception handler fails to update the PC to the
instruction after the excepting instruction when returning, the exception executes again.
Any of the following actions prevent taking the exception again:
• Clearing FPSR[NAN]
• Disabling FPCR[BSUN]
• Incrementing the stored PC in the stack bypasses the conditional instruction. This

applies to situations where fall-through is desired. Note that to accurately calculate the
PC increment requires knowledge of the size of the bypassed conditional instruction.

Table 6-13. INAN Exception Enabled/Disabled Results

Condition

INAN Description

Exception

disabled

0

If the destination data format is single- or double-precision, a NAN is generated with a
mantissa of all ones and a sign of zero transferred to the destination. If the destination data
format is B, W, or L, a constant of all ones is written to the destination.

Exception

enabled

1

The result written to the destination is the same as the exception disabled case unless the
exception occurs on a FMOVE OUT, in which case the destination is unaffected.

Table 6-14. IDE Exception Enabled/Disabled Results

Condition

IDE

Description

Exception

disabled

0

Any denormalized operand is treated as zero, FPSR[INEX] is set, and the operation
proceeds.

Exception

enabled

1

The result written to the destination is the same as the exception disabled case unless the
exception occurs on a FMOVE OUT, in which case the destination is unaffected.
FPSR[INEX] is not set to allow the handler to set it appropriately.

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