Freescale Semiconductor MCF5480 - Manual (Page 234)

MCF548x Reference Manual, Rev. 3
7-14 Freescale Semiconductor
an exception aborts the instruction and the data may be accessed again when the instruction is restarted.
These guarantees apply only when ACRn[CM] indicates precise mode and aligned accesses.
CPU space-register accesses using the MOVEC instruction are treated as cache-inhibited and precise.
7.9.2 Cache Protocol
The following sections describe the cache protocol for processor accesses and assumes that the data is
cacheable (that is, write-through or copyback). Note that the discussion of write operations applies to the
data cache only.
7.9.2.1 Read Miss
A processor read that misses in the cache requests the cache controller to generate a bus transaction. This
bus transaction reads the needed line from memory and supplies the required data to the processor core.
The line is placed in the cache in the valid state.
7.9.2.2 Write Miss (Data Cache Only)
The cache controller handles processor writes that miss in the data cache differently for write-through and
copyback regions. Write misses to copyback regions cause the cache line to be read from system memory,
as shown in Figure 7-6 .
Figure 7-6. Write-Miss in Copyback Mode
The new cache line is then updated with write data and the M bit is set for the line, leaving it in modified
state. Write misses to write-through regions write directly to memory without loading the corresponding
cache line into the cache.
Cache Line
System V = 1
M = 0
1. Writing character X to 0x0B generates a write miss. Data cannot be written to an invalid line.
Memory
V = 0
M = 0
0x0C 0x00 0x08 0x04
2. The cache line (characters A–P) is updated from system memory, and the line is marked valid.
X
ABCD EFGH IJKL MNOP
3. After the cache line is filled, the write that initiated the write miss (the character X) completes to 0x0B.
V = 1
M = 1
0x0C 0x00 0x08 0x04
0x0C 0x00 0x08 0x04
ABCD EXGH IJKL MNOP
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