Freescale Semiconductor MCF5480 - Manual (Page 243)

Cache Management
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 7-23
7.11 Cache Management
The cache can be enabled and configured by using a MOVEC instruction to access CACR. A hardware
reset clears CACR, disabling the cache and removing all configuration information; however, reset does
not affect the tags, state information, and data in the cache.
Set CACR[DCINVA,ICINVA] to invalidate the caches before enabling them.
The privileged CPUSHL instruction supports cache management by selectively pushing and invalidating
cache lines. The address register used with CPUSHL directly addresses the cache’s directory array. The
CPUSHL instruction flushes a cache line.
The value of CACR[DDPI,IDPI] determines whether CPUSHL invalidates a cache line after it is pushed.
To push the entire cache, implement a software loop to index through all sets and through each of the four
lines within each set (a total of 512 lines for the data cache and 1024 lines for the instruction cache). The
state of CACR[DEC,IEC] does not affect the operation of CPUSHL or CACR[DCINVA,ICINVA].
Disabling a cache by setting CACR[IEC] or CACR[DEC] makes the cache nonoperational without
affecting tags, state information, or contents.
14–13 S Supervisor mode. Specifies whether only user or supervisor accesses are allowed in this address
range or if the type of access is a don’t care.
00 Match addresses only in user mode
01 Match addresses only in supervisor mode
1x Execute cache matching on all accesses
12–11 — Reserved, should be cleared.
10 AMM Address mask mode.
0 The ACR hit function allows control of a 16 Mbytes or greater memory region.
1 The upper 8 bits of the address and ACR are compared without a mask function. Address bits
[23:20] of the address and ACR are compared using ACR[19:16] as a mask, allowing control of
a 1–16 Mbyte memory region.
9–7 — Reserved; should be cleared.
6–5 CM Cache mode. Selects the cache mode and access precision. Precise and imprecise modes are
described in
Section 7.9.1.2, “Cache-Inhibited Accesses .”
00 Cacheable, write-through
01 Cacheable, copyback
10 Cache-inhibited, precise
11 Cache-inhibited, imprecise
4 — Reserved, should be cleared.
3 SP Supervisor protect.
0 Indicates supervisor and user mode access allowed, reset value is 0
1 Indicates only supervisor access is allowed to this address space and attempted user mode
accesses generate an access error exception
2 W ACR0/ACR1 only. Write protect. Selects the write privilege of the memory region. ACR2[W] and
ACR3[W] are reserved.
0 Read and write accesses permitted
1 Write accesses not permitted
1–0 — Reserved, should be cleared.
Table 7-5. ACRn Field Descriptions (Continued)
Bits Name Description