Freescale Semiconductor MCF5480 - Manual (Page 247)

Cache Operation Summary
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 7-27
7.12.2 Data Cache State Transitions
Using the V and M bits, the data cache supports a line-based protocol allowing individual cache lines to
be invalid, valid, or modified. To maintain memory coherency, the data cache supports both write-through
and copyback modes, specified by the corresponding ACR[CM], or CACR[DDCM] if no ACR matches.
Read or write misses to copyback regions cause the cache controller to read a cache line from memory into
the cache. If available, tag and data from memory update an invalid line in the selected set. The line state
then changes from invalid to valid by setting the V bit. If all lines in the row are already valid or modified,
the pseudo-round-robin replacement algorithm selects one of the four lines and replaces the tag and data.
Before replacement, modified lines are temporarily buffered and later copied back to memory after the
new line has been read from memory.
Figure 7-13 shows the three possible data cache line states and possible processor-initiated transitions for
memory configured as copyback. Transitions are labeled with a capital letter indicating the previous state
and a number indicating the specific case; see Table 7-7 .
Figure 7-13. Data Cache Line State Diagram—Copyback Mode
Figure 7-14 shows the two possible states for a cache line in write-through mode.
Figure 7-14. Data Cache Line State Diagram—Write-Through Mode
Table 7-7 describes data cache line transitions and the accesses that cause them.
Invalid
CD1—CPU
CI3—CPU
Valid
V = 1
Modified
read miss
write miss
CI5—DCINVA
CI6—CPUSHL & DDPI
CI7—CPUSHL & DDPI CV1—CPU read miss
CV2—CPU read hit
CV7—CPUSHL & DDPI
CD2—CPU read hit
CD3—CPU write miss
CD4—CPU write hit
CD5—DCINVA
CD6—CPUSHL & DDPI
CV3—CPU write miss
CV4—CPU write hit
CI1—CPU read miss
CV5—DCINVA
CV6—CPUSHL & DDPI
V = 0
M = 0
V = 1
M = 1
CD7—CPUSHL
& DDPI
WI1—CPU read miss
Invalid Valid
WI3—CPU write miss
WI5—DCINVA
WI6—CPUSHL & DDPI
WV1—CPU read miss
WV2—CPU read hit
WV3—CPU write miss
WV4—CPU write hit
WV7—CPUSHL & DDPI
WV5—DCINVA
WV6—CPUSHL & DDPI
V = 0 V = 1