Freescale Semiconductor MCF5480 - Manual (Page 252)

MCF548x Reference Manual, Rev. 3
8-2 Freescale Semiconductor
generations of ColdFire cores. For Revision A, CSR[HRL] is 0. See Section 8.4.2, “Configuration/Status
Register (CSR) .”
The Version 3 core implements Revision B of the debug architecture, offering more flexibility for
configuring the hardware breakpoint trigger registers and removing the restrictions involving concurrent
BDM processing while hardware breakpoint registers are active. For Revision B, CSR[HRL] is 1.
Revision C of the debug architecture more than doubles the on-chip breakpoint registers and provides an
ability to interrupt debug service routines. For Revision C, CSR[HRL] is 2.
Differences between Revision B and C are summarized as follows:
• Debug Revision B has separate PST[3:0] and DDATA[3:0] signals.
• Debug Revision C adds breakpoint registers and supports normal interrupt request service during
debug. It combines debug signals into PSTDDATA[7:0].
The addition of the memory management unit (MMU) to the baseline architecture requires corresponding
enhancements to the ColdFire debug functionality, resulting in Revision D. For Revision D, the revision
level bit, CSR[HRL], is 3.
With software support, the MMU can provide a demand-paged, virtual address environment. To support
debugging in this virtual environment, the debug enhancements are primarily related to the expansion of
the virtual address to include the 8-bit address space identifier (ASID). Conceptually, the virtual address
is expanded to a 40-bit value: the 8-bit ASID plus the 32-bit address.
The expansion of the virtual address affects two major debug functions:
• The ASID is optionally included in the specification of the hardware breakpoint registers. As an
example, the four PC breakpoint registers are each expanded by 8 bits, so that a specific ASID
value may be programmed as part of the breakpoint instruction address. Likewise, each operand
address/data breakpoint register is expanded to include an ASID value. Finally, new control
registers define if and how the ASID is to be included in the breakpoint comparison trigger logic.
• The debug module implements the concept of ownership trace in which the ASID value may be
optionally displayed as part of the real-time trace functionality. When enabled, real-time trace
displays instruction addresses on every change-of-flow instruction that is not absolute or
PC-relative. For Rev. D, this instruction address display optionally includes the contents of the
ASID, thus providing the complete instruction virtual address on these instructions.
Additionally when a Sync_PC serial BDM command is loaded from the external development
system, the processor optionally displays the complete virtual instruction address, including the
8-bit ASID value.
In addition to these ASID-related changes, the new MMU control registers are accessible by using serial
BDM commands. The same BDM access capabilities are also provided for the EMAC and FPU
programming models.
Finally, a new serial BDM command is implemented (FORCE_TA) to assist debugging when a software
error generates an incorrect memory address that hangs the external bus. The new BDM command
attempts to break this condition by forcing a bus termination.
8.2 Signal Descriptions
Table 8-1 describes debug module signals. All ColdFire debug signals are unidirectional and related to a
rising edge of the processor core’s clock signal. The standard 26-pin debug connector is shown in
Section 8.9, “Freescale-Recommended BDM Pinout .”