Freescale Semiconductor MCF5480 - Manual (Page 271)

Memory Map/Register Definition
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 8-21
Figure 8-12 shows PBMR. PBMR is accessible in supervisor mode as debug control register 0x09 using
the WDEBUG instruction and via the BDM port using the WDMREG command.
Table 8-14 describes PBMR fields.
8.4.8 Address Breakpoint Registers (ABLR/ABLR1, ABHR/ABHR1)
The ABLR, ABLR1, ABHR, and ABHR1, shown in Figure 8-13 , define regions in the processor’s data
address space that can be used as part of the trigger. These register values are compared with the address
for each transfer on the processor’s high-speed local bus. The trigger definition register (TDR) identifies
the trigger as one of three cases:
• Identically the value in ABLR
• Inside the range bound by ABLR and ABHR inclusive
• Outside that same range
XTDR determines the same for ABLR1 and ABHR1.
Table 8-13. PBR, PBR1, PBR2, PBR3 Field Descriptions
Bits Name Description
31–1 CNTRAD PC breakpoint address. The 31-bit address to be compared with the PC as a breakpoint
trigger.
0 V Valid.
0 Breakpoint registers are not compared with the processor’s program counter register
1 Breakpoint registers are compared with the processor’s program counter register when
the appropriate valid bit is set and TDR or XTDR are configured appropriately.
Note: This bit is not implemented on PBR0; it is implemented on PBR[1:3].
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R CNTRMSK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R CNTRMSK
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Reg
Addr
CPU + 0x09
Figure 8-12. Program Counter Breakpoint Mask Register (PBMR)
Table 8-14. PBMR Field Descriptions
Bits Name Description
31–0 CNTRMSK PC breakpoint mask.
0 This PBMR bit causes the corresponding PBR bit to be compared to the appropriate
program counter register bit.
1 This PBMR bit causes the corresponding PBR bit to be ignored.