Freescale Semiconductor MCF5480 - Manual (Page 281)

Background Debug Mode (BDM)
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 8-31
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Table 8-22 describes receive BDM packet fields.
8.5.2.2 Transmit Packet Format
The basic transmit packet, Figure 8-20 , consists of 16 data bits and 1 control bit.
Table 8-23 describes transmit BDM packet fields.
8.5.3 BDM Command Set
Table 8-24 summarizes the BDM command set. Subsequent paragraphs contain detailed descriptions of
each command. Issuing a BDM command when the processor is accessing debug module registers using
the WDEBUG instruction causes undefined behavior.
16 15 0
S Data Field [15:0]
Figure 8-19. Receive BDM Packet
Table 8-22. Receive BDM Packet Field Description
Bits Name Description
16 S Status. Indicates the status of CPU-generated messages listed below. The not-ready response can
be ignored unless a memory-referencing cycle is in progress. Otherwise, the debug module can
accept a new serial transfer after 32 processor clock periods.
S DataMessage
0 xxxx Valid data transfer
0 0xFFFFStatus OK
1 0x0000Not ready with response; come again
1 0x0001Error: Terminated bus cycle; data invalid
1 0xFFFFIllegal command
15–0 Data Data. Contains the message to be sent from the debug module to the development system. The
response message is always a single word, with the data field encoded as shown above.
16 15 0
C D[15:0]
Figure 8-20. Transmit BDM Packet
Table 8-23. Transmit BDM Packet Field Description
Bits Name Description
16 C Control. This bit is reserved. Command and data transfers initiated by the development
system should clear C.
15–0 Data Contains the data to be sent from the development system to the debug module.