Freescale Semiconductor MCF5480 - Manual (Page 303)

Real-Time Debug Support
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 8-53
4. It executes an RTE instruction when the exception handler finishes. During the processing of the
RTE, FS1 is reloaded from the system stack. If this bit is set, the processor sets the emulator mode
state and resumes execution of the original debug interrupt service routine. This is signaled
externally by the generation of the PST value that originally identified the debug interrupt
exception, that is, PST = 0xD.
Fault status encodings are listed in Table 5-2 . Implementation of this debug interrupt handling fully
supports the servicing of a number of normal interrupt requests during a debug interrupt service routine.
The emulator mode state bit is essentially changed to be a program-visible value, stored into memory
during exception stack frame creation, and loaded from memory by the RTE instruction.
When debug interrupt operations complete, the RTE instruction executes and the processor exits emulator
mode. After the debug interrupt handler completes execution, the external development system can use
BDM commands to read the reserved memory locations.
In Revision A, if a hardware breakpoint such as a PC trigger is left unmodified by the debug interrupt
service routine, another debug interrupt is generated after the completion of the RTE instruction. In
Revisions B and C, the generation of another debug interrupt during the first instruction after the RTE exits
emulator mode is inhibited. This behavior is consistent with the existing logic involving trace mode where
the first instruction executes before another trace exception is generated. Thus, all hardware breakpoints
are disabled until the first instruction after the RTE completes execution, regardless of the programmed
trigger response.
8.6.1.1 Emulator Mode
Emulator mode is used to facilitate nonintrusive emulator functionality. This mode can be entered in three
different ways:
• Setting CSR[EMU] forces the processor into emulator mode. EMU is examined only if RSTI is
negated and the processor begins reset exception processing. It can be set while the processor is
halted before reset exception processing begins. See Section 8.5.1, “CPU Halt .”
• A debug interrupt always puts the processor in emulation mode when debug interrupt exception
processing begins.
• Setting CSR[TRC] forces the processor into emulation mode when trace exception processing
begins.
While operating in emulation mode, the processor exhibits the following properties:
• Unmasked interrupt requests are serviced. The resulting interrupt exception stack frame has FS[1]
set to indicate the interrupt occurred while in emulator mode.
• If CSR[MAP] = 1, all caching of memory and the SRAM module are disabled. All memory
accesses are forced into a specially mapped address space signaled by TT = 0x2, TM = 0x5 or 0x6.
This includes stack frame writes and the vector fetch for the exception that forced entry into this
mode.
The RTE instruction exits emulation mode. The processor status output port provides a unique encoding
for emulator mode entry (0xD) and exit (0x7).
8.6.2 Concurrent BDM and Processor Operation
The debug module supports concurrent operation of both the processor and most BDM commands. BDM
commands may be executed while the processor is running, except the following:
• Read/write address and data registers