Freescale Semiconductor MCF5480 - Manual (Page 304)

MCF548x Reference Manual, Rev. 3
8-54 Freescale Semiconductor
• Read/write control registers
For BDM commands that access memory, the debug module requests the processor’s local bus. The
processor responds by stalling the instruction fetch pipeline and waiting for current bus activity to
complete before freeing the local bus for the debug module to perform its access. After the debug module
bus cycle, the processor reclaims the bus.
NOTE
Breakpoint registers must be carefully configured in a development system
if the processor is executing. The debug module contains no hardware
interlocks, so TDR and XTDR should be disabled while breakpoint registers
are loaded, after which TDR and XTDR can be written to define the exact
trigger. This prevents spurious breakpoint triggers.
Because there are no hardware interlocks in the debug unit, no BDM operations are allowed while the CPU
is writing the debug’s registers (DSCLK must be inactive).
8.7 Debug C Definition of PSTDDATA Outputs
This section specifies the ColdFire processor and debug module’s generation of the PSTDDATA output on
an instruction basis. In general, the PSTDDATA output for an instruction is defined as follows:
PSTDDATA = 0x1, {[0x89B], operand}
where the {...} definition is optional operand information defined by the setting of the CSR.
The CSR provides capabilities to display operands based on reference type (read, write, or both). A PST
value {0x8, 0x9, or 0xB} identifies the size and presence of valid data to follow on the PSTDDATA output
{1, 2, or 4 bytes}. Additionally, for certain change-of-flow branch instructions, CSR[BTB] provides the
capability to display the target instruction address on the PSTDDATA output {2, 3, or 4 bytes} using a PST
value of {0x9, 0xA, or 0xB}.
8.7.1 User Instruction Set
Table 8-30 shows the PSTDDATA specification for user-mode instructions. Rn represents any {Dn, An}
register. In this definition, the ‘y’ suffix generally denotes the source and ‘x’ denotes the destination
operand. For a given instruction, the optional operand data is displayed only for those effective addresses
referencing memory.
Table 8-30. PSTDDATA Specification for User-Mode Instructions
Instruction Operand Syntax PSTDDATA
add.l <ea>y,Dx PSTDDATA = 0x1,{0xB, source operand}
add.l Dy,<ea>x PSTDDATA = 0x1,{0xB, source},{0xB, destination}
adda.l <ea>y,Ax PSTDDATA = 0x1,{0xB, source operand}
addi.l #<data>,Dx PSTDDATA = 0x1
addq.l #<data>,<ea>x PSTDDATA = 0x1,{0xB, source},{0xB, destination}
addx.l Dy,Dx PSTDDATA = 0x1
and.l <ea>y,Dx PSTDDATA = 0x1,{0xB, source operand}
and.l Dy,<ea>x PSTDDATA = 0x1,{0xB, source},{0xB, destination}