Freescale Semiconductor MCF5480 - Manual (Page 317)

MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 9-1
Chapter 9
System Integration Unit (SIU)
9.1 Introduction
The system integration unit (SIU) of the MCF548x family integrates several timer functions required by
most embedded systems. The SIU contains the following components:
• Slice timers
• Watchdog timer
• General purpose timers
• General purpose I/O ports
• Interrupt controller
Two internal 32-bit slice timers are provided to create short cycle periodic interrupts, typically utilized for
RTOS scheduling and alarm functionality. A watchdog timer is included that will reset the processor if not
regularly serviced, catching software hang-ups. Up to four 32-bit general purpose timers are included,
which are capable of input capture, output compare, and PWM functionality. Most peripheral I/O pins on
the MCF548x family are muxed with GPIO, adding flexibility and usability to pins on the chip.
The programmable interrupt controller multiplexes the external interrupts, general purpose timers, slice
timers, and peripheral sources to the CF4e core. Refer to Chapter 13, “Interrupt Controller,” for
information about the MCF548x interrupt controller.
The SIU timers are discussed in the following chapters:
• General purpose timers and watchdog timer (GPT0) are described in Chapter 11, “General Purpose
Timers (GPT).”
— The watchdog timer is further detailed in Section 10.3.2.3, “Watchdog Functions.”
• Slice timers are detailed in Chapter 12, “Slice Timers (SLT).”
• GPIO functionality is discussed in Chapter 15, “GPIO.”
9.2 Features
The system integration unit has the following features:
• Interrupt controller
• Two 32-bit slice timers for periodic alarm and interrupt generation
• Software watchdog timer with programmable secondary bus monitor
• Up to four 32-bit general-purpose timers with capture, compare, and PWM capability
• General-purpose I/O ports multiplexed with peripheral pins
• System protection and reset status and control
9.3 Memory Map/Register Definition
Table 9-1 shows the programming model for the SIU.