Freescale Semiconductor MCF5480 - Manual (Page 325)

Introduction
MCF548x Reference Manual, Rev. 3
Freescale Semiconductor 10-3
• CommBus — The data transfer interface between the multichannel DMA and each peripheral
function.
10.1.4 XL Bus Features
Features of the XL bus and its integration modules include the following:
• 32-bit physical address
• 64-bit data bus width
• Split-transaction bus; address and data tenures occur independently.
• One-level address pipeline; supports up to two complete address tenures before the first data tenure
completes.
• Strict, in-order, address and data tenures are enforced.
• Address and data bus “parking” may be used to remove arbitration phase from the address and data
tenures—most recent master, programmed master, or no parking methods supported.
• Access can occur in single (1-8 bytes) beat, or four-beat (32 bytes) burst transfers.
• Eight-level arbitration priority that is hardware selectable for each master with a least recently used
(LRU) protocol for masters of equal priority. Priority may change dynamically based on specific
system requirements.
• Fully static, multiplexed bus architecture.
10.1.5 Internal Bus Transaction Summaries
The XL bus can be mastered by the ColdFire core, multichannel DMA controller, and the PCI controller
(external PCI master). Any of these masters can access all resources available to the XL bus.
Bus masters can access any on-chip or off-chip resources via the XL bus. The sequence is as follows:
• Bus masters gains mastership of the XL bus from the XL bus arbiter.
• The bus master’s address is asserted during the address tenure. XL bus slave devices (SDRAM,
PCI, etc.) decode the address. If the address falls within a slave’s space, it returns an address
acknowledge.
• The bus master initiates the data tenure and transfers the data to the appropriate slave device.
10.1.6 XL Bus Interface Operations
This section describes how the XLB interface operates.
10.1.6.1 Basic Transfer Protocol
An XLB interface memory transaction is illustrated in Figure 10-3 . It shows that the transaction consists
of distinct address and data tenures, each having three phases: arbitration, transfer, and termination. The
separation of these operations allows address pipelines and split transactions to be implemented.
Split-bus transaction capability allows one master to have mastership of the address bus, while another
master has mastership of the data bus. Pipelines allows the address tenure of a bus transaction to begin
before the data tenure of the previous transaction finishes.
The data transfer phase can either be one beat or four, depending on whether or not the transaction is a
burst.